CS5535 datasheet(507/555 Pages) NSC

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Flash Controller Register Descriptions (Continued)

5.19.1.5

Flash Reserved (NANDF_RSVD)

This register is reserved. Reads return 0. Writes have no effect.

5.19.2 Flash Controller Native Registers

5.19.2.1

NAND Device Data (NAND_DATA)

Reading or writing to this range accesses the same NAND Device Data.

10:8

tCH

Control Hold Time. The hold time from the rising edge of WE# to the toggle of control

signals. Note that the I/O bus is turned off when the tCH expires. Range = 0h to 7h.

Refer to Figure 4-59 "NAND Flash Command/Address Timing" on page 174.

RSVD

Reserved. Reads return value written.

6:4

tCP

Control Pulse Width. The WE# active pulse width in command/address phase. Note

that the command/address byte is put on the I/O bus at the same time that the WE# is

asserted. Range = 1h to 7h. Refer to Figure 4-59 "NAND Flash Command/Address

Timing" on page 174.

RSVD

Reserved. Reads return value written.

2:0

tCS

Control Setup Time. The setup time from the toggle of the control signals to the WE#

falling edge. Range = 0h to 7h. Refer to Figure 4-59 "NAND Flash Command/Address

Timing" on page 174.

MSR Address

5140001Dh

Type

R/W

Reset Value

00000000h

Flash Memory Offset 000h-7FFh

Flash I/O Offset

00h-03h

Type

R/W

Reset Value

Undefined

NAND_DATA Register Map

76543

210

DATA

NAND_DATA Bit Descriptions

Bit

Name

Description

7:0

DATA

NAND Device Data. No default value. This address space is not to be read from

until

data is read from the NAND Flash device. The system will hang if a read is done from

this address space without a prior read from NAND Flash device.

NANDF_CTL Bit Descriptions

Bit

Name

Description

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