CS5535 datasheet(508/555 Pages) NSC

508 / 555 page

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508

Revision 0.8

Flash Controller Register Descriptions (Continued)

5.19.2.2

NAND Control Register (NAND_CTL)

5.19.2.3

NAND I/O (NAND_IO)

Flash Memory Offset Any Even Address between 800h-80Eh

Flash I/O Offset

04h

Type

R/W

Reset Value

01h

NAND_CTL Register Map

76543

210

RSVD

DIST_EN

RDY_INT_

MASK

ALE

CLE

CE#

NAND_CTL Bit Descriptions

Bit

Name

Description

7:5

RSVD (RO)

Reserved (Read Only). Returns 0 when read.

4DIST_EN

NAND Distract Interrupt Enable.

0: Disables the generation of NAND Distract Interrupt.

1: Enables the generation of NAND Distract Interrupt.

RDY_INT_MASK

NAND Ready Interrupt Mask.

0: Interrupt is masked.

1: Enable NAND Flash device’s RDY/BUSY# signal to generate an interrupt.

2ALE

Address Latch Enable. FLASH_ALE output signal reflects the value of this bit.

1CLE

Command Latch Enable. FLASH_CLE output signal reflects the value of this bit.

0CE#

Chip Enable. CE# signal reflects the value of this bit. The NAND_CS signals from the

Diverse Device determine which CE# is asserted. Keep this bit low during entire NAND

cycle. Writing a 1 to this bit resets the NAND controller.

Flash Memory Offset Any Odd Address between 801h-80Fh

Flash I/O Offset

05h

Type

R/W

Reset Value

00h

NAND_IO Register Map

76543

210

NAND_IO Bit Descriptions

Bit

Name

Description

7:0

I/O Register. Writing to this register triggers a command/address phase sub-cycle on

the NAND Flash interface. The data written to this register is put on the I/O bus during

the sub-cycle. It returns previous written value when read.

Note:

Before writing to this register check for CTLR_BUSY bit (Flash Memory Offset

810h[2]/Flash I/O Offset 06h[2]) in NAND_STS register to be 0.

CS5535 Datasheet(PDF) 508 Page - National Semiconductor (TI)

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