CS5535 datasheet(506/555 Pages) NSC

506 / 555 page

www.national.com

506

Revision 0.8

Flash Controller Register Descriptions (Continued)

the valid range for the count values of pulse width in NAND MSRs is 1 through 7 Local Bus clock (‘lb_c’) cycles or LPC

clock (‘lpc_c’) cycles.

5.19.1.4

NAND Flash Control Timing (NANDF_CTL)

NANDF_DATA Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9876543210

RSVD

tRH

tRP

tRS

RSVD

tWH

tWP

tWS

NANDF_DATA Bit Descriptions

Bit

Name

Description

31:27

RSVD

Reserved. Reads return value written.

26:24

tRH

Data Read Hold Time. This timing is just for internal state machine; no external refer-

ence point. Can be set to 0 if the hold time is not needed. Range = 0h to 7h. Refer to

Figure 4-61 "NAND Data Timing with Wait States" on page 175.

RSVD

Reserved. Reads return value written.

22:20

tRP

Data Read Pulse Width. The RE# active pulse width in data read phase. Range = 1h

to 7h. Refer to Figure 4-61 "NAND Data Timing with Wait States" on page 175.

RSVD

Reserved. Reads return value written.

18:16

tRS

Data Read Setup Time. This timing is just for internal state machine; no external refer-

ence point. Can be set to 0 if the setup time is not needed. Range = 0h to 7h. Refer to

Figure 4-61 "NAND Data Timing with Wait States" on page 175.

15:11

RSVD

Reserved. Reads return value written.

10:8

tWH

Data Write Hold Time. The hold time from WE# rising edge to I/O bus is turned off.

Range = 0h to 7h. Refer to Figure 4-61 "NAND Data Timing with Wait States" on page

175.

RSVD

Reserved. Reads return value written.

6:4

tWP

Data Write Pulse Width. The WE# active pulse width in data write phase. Note that

the data byte is put on the I/O bus at the same time the WE# is asserted. Range = 1h to

7h. Refer to Figure 4-61 "NAND Data Timing with Wait States" on page 175.

RSVD

Reserved. Reads return value written.

2:0

tWS

Data Write Setup Time. This timing is just for internal state machine; no external refer-

ence point. Can be set to 0 if the setup time is not needed. Range = 0h to 7h. Refer to

Figure 4-61 "NAND Data Timing with Wait States" on page 175.

MSR Address

5140001Ch

Type

R/W

Reset Value

00000777h

NANDF_CTL Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9876543210

RSVD

tCH

tCP

tCS

NANDF_CTL Bit Descriptions

Bit

Name

Description

31:11

RSVD

Reserved. Reads return value written.

CS5535 Datasheet(PDF) 506 Page - National Semiconductor (TI)

CS5535 Datasheet(HTML) 506 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL