CS5535 datasheet(503/555 Pages) NSC

503 / 555 page

Revision 0.8

503

www.national.com

Flash Controller Register Descriptions (Continued)

CHK_IOCHRDY3

(Note 1)

Check I/O Channel Ready 3. Check FLASH_IOCHRDY signal for NOR Chip Select #3

(FLASH_CS3#)

0: Ignore IOCHRDY signal. No wait states will be inserted.

1: Check IOCHRDY before finishing the chip select strobe pulse.

CHK_IOCHRDY2

(Note 1)

Check I/O Channel Ready 2. Check FLASH_IOCHRDY signal for NOR Chip Select #2

(FLASH_CS2#)

0: Ignore IOCHRDY signal. No wait states will be inserted.

1: Check IOCHRDY before finishing the chip select strobe pulse.

CHK_IOCHRDY1

(Note 1)

Check I/O Channel Ready 1. Check FLASH_IOCHRDY signal for NOR Chip Select #1

(FLASH_CS1#)

0: Ignore IOCHRDY signal. No wait states will be inserted.

1: Check IOCHRDY before finishing the chip select strobe pulse.

CHK_IOCHRDY0

(Note 1)

Check I/O Channel Ready 0. Check FLASH_IOCHRDY signal for NOR Chip Select #0

(FLASH_CS0#)

0: Ignore IOCHRDY signal. No wait states will be inserted.

1: Check IOCHRDY before finishing the chip select strobe pulse.

3WE_CS3

Write Enable for CS3#. Write Enable for NOR Chip Select #3 (FLASH_CS3#)

0: No write cycles go out to NOR Flash interface via CS3#.

1: Allow write cycles to go out to NOR Flash interface.

2WE_CS2

Write Enable for CS2#. Write Enable for NOR Chip Select #2 (FLASH_CS2#)

0: No write cycles go out to NOR Flash interface via CS2#.

1: Allow write cycles to go out to NOR Flash interface.

1WE_CS1

Write Enable for CS1#. Write Enable for NOR Chip Select #1 (FLASH_CS1#)

0: No write cycles go out to NOR Flash interface via CS1#.

1: Allow write cycles to go out to NOR Flash interface.

0WE_CS0

Write Enable for CS0#. Write Enable for NOR Chip Select #0 (FLASH_CS0#)

0: No write cycles go out to NOR Flash interface via CS0#.

1: Allow write cycles to go out to NOR Flash interface.

Note 1. If any CHK_IOCHRDY[x] bit (bits [7:4]) is high, and the corresponding Chip Select (FLASH_CS[x]#) is low, then

signal FLASH_IOCHRDY is checked to determine when to de-assert the RE# or WE# strobe. The RE# or WE#

strobe pulse width will be the programmed value (MSR_NORTF_T01[22:20], MSR_NORTF_T01[6:4],

MSR_NORTF_T23[22:20] and MSR_NORTF_T23[6:4]

) increased by at least two local bus clock (33 MHz) cycles.

If no CHK_IOCHRDY[x] bit (bits [7:4]) is high, or if no CHK_IORDY[x] bit is high that has a corresponding active

(low) Chip Select (FLASH_CS[x]#), then signal FLASH_IOCHRDY is ignored and the NOR Controller’s WE# and

RE# strobe pulse widths will be the values programmed in the NOR MSR registers (MSR_NORTF_T01[22:20],

MSR_NORTF_T01[6:4], MSR_NORTF_T23[22:20] and MSR_NORTF_T23[6:4]

). In this case, if the pulse width of

WE# and RE# in the NOR MSR registers is programmed as 0, then the NOR Controller’s WE# and RE# generation

will use 16 as the count value of NOR pulse width.

NORF_CTL Bit Descriptions

Bit

Name

Description

CS5535 Datasheet(PDF) 503 Page - National Semiconductor (TI)

CS5535 Datasheet(HTML) 503 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL