CS5535 datasheet(501/555 Pages) NSC

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5.19 FLASH CONTROLLER REGISTER DESCRIPTIONS

The registers for the Flash Controller are divided into three

sets:

• Standard GeodeLink Device MSRs (Shared with DIVIL,

see Section 5.6.1 on page 299.)

• Flash Controller Specific MSRs

• Flash Controller Native Registers

The MSRs are accessed via the RDMSR and WRMSR pro-

cessor instructions. The MSR address is derived from the

perspective of the CPU Core. See Section 3.2 "CS5535

MSR Addressing" on page 53 for more details on MSR

addressing.

All MSRs are 64 bits, however, the Flash Controller Spe-

cific MSRs (summarized in Table 5-69) are called out as 32

bits. The Flash Controller treats writes to the upper 32 bits

(i.e., bits [63:32]) of the 64-bit MSRs as don’t cares and

always returns 0 on these bits.

The Native registers associated with the Flash Controller

are NAND configuration registers, summarized in Table 5-

70. The NAND native registers are 4-kbyte memory

mapped or 16-byte I/O mapped. The base address is

defined by LBAR in Diverse Device and can be located at

any 4-kbyte boundaries if it is memory mapped, any 16-

byte boundary if it is I/O mapped. The NAND Flash Con-

troller is a 32-bit wide device present in Diverse Device

without burst capability. To access the MSR registers in the

NAND Flash Controller, a 32-bit wide bus is used as the

LBus interface. For NAND Command/Address, data write

and read modes, the NAND Flash Controller provides the

valid data on the least significant nibbles of the LBus data

ports.

There are no NOR control registers located in I/O or mem-

ory space. All NOR timing control functions are located in

the Flash Specific MSRs. Additionally, the Diverse Device

LBAR MSRs associates up to four chip selects for four

Flash devices (see Section 5.6.2.9 "Local BAR - Flash Chip

Select (DIVIL_LBAR_FLSH[x])" on page 313 bit details).

• MSR_LBAR_FLSH0 (MSR 51400010h) for use with

FLASH_CS0#.

• MSR_LBAR_FLSH1 (MSR 51400011h) for use with

FLASH_CS1#.

• MSR_LBAR_FLSH2 (MSR 51400012h) for use with

FLASH_CS2#.

• MSR_LBAR_FLSH3 (MSR 51400013h) for use with

FLASH_CS3#.

After the MSR setup is complete, a NOR Flash device can

be associated with a block of system memory using up to

28 address bits (A[27:0]).

The reference column in the summary tables point to the

page where the register maps and bit descriptions are

listed.

Table 5-69. Flash Controller Specific MSRs Summary

MSR

Address

Type

Reset

Value

Reference

51400018h

R/W

NOR Flash Control (NORF_CTL)

00000000h

Page 502

51400019h

R/W

NOR Flash Timing for Chip Selects 0 and 1 (NORTF_T01)

07770777h

Page 504

5140001Ah

R/W

NOR Flash Timing for Chip Selects 2 and 3 (NORTF_T23)

07770777h

Page 505

5140001Bh

R/W

NAND Flash Data Timing MSR (NANDF_DATA)

07770777h

Page 505

5140001Ch

R/W

NAND Flash Control Timing (NANDF_CTL)

00000777h

Page 505

5140001Dh

R/W

Flash Reserved (NANDF_RSVD)

00000000h

Page 505

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