CS5535 datasheet(549/555 Pages) NSC

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Electrical Specifications (Continued)

6.3.14 MFGPT Signaling

The MFGPT signals detailed in this sub-section use vari-

ous types of buffers depending upon chip configuration. For

a detailed explanation of buffer types, see Table 2-4 "Buffer

Type Characteristics" on page 28.

In this subsection, unless otherwise noted:

• All timing specifications are specified under the oper-

ating conditions listed in Table 6-3 on page 526 (i.e.,

VCORE and VCORE_VSB = All; VIO and VIO_VSB = All;

TCASE = All).

• MFGPT signals are referenced to KHZ32_XCI or

MHZ14_CLK depending on MFGPT clock configuration.

Use low-to-high edge if MHZ14_CLK; use high-to-low

edge if KHZ32_XCI. MFGPT7 supports KHZ32_XCI

only.

• MFPGT signal parameters are defined in Figure 6-2 "AC

Reference Timing and Test Definition" on page 530.

Table 6-22. MFGPT Signaling

Signal

Parameter

Min

Max

Units

Comment/Condition

Inputs:

MFGPT0 (GPIO6)

MFGPT1 (GPIO5)

MFGPT2 (GPIO21)

MFGPT7 (GPIO26)

Async Input

No clock reference.

Restarts the MFGPT.

Note 1 and Note 2.

Outputs:

MFGPT0_C1 (GPIO5)

MFGPT1_C1 (GPIO6)

MFGPT2_C1 (GPIO7)

MFGPT7_C1 (GPIO27)

tVAL if MHZ14_CLK

Note 2, Note 3, and Note 4.

tVAL if KHZ32_XCI

Outputs:

MFGPT0_C2 (GPIO1)

MFGPT1_C2 (GPIO11)

MFGPT2_C2 (GPIO6)

MFGPT7_C2 (GPIO25)

tVAL if MHZ14_CLK

Note 2, Note 3, and Note 5.

tVAL if KHZ32_XCI

Note 1. GPIO configured: Input Enable and AUX_IN = 1; Output Enable,

AUX_OUT_1, and AUX_OUT_2 = 0.

Note 2. PIN_OPT_LALL = 0 in Table 2-6 "DIVIL_BALL_OPT" on page 29.

Note 3. tVAL min times with load of: 10 pF cap to ground.

tVAL max times with load of: 50 pF cap to ground.

Note 4. GPIO configured: AUX_IN, Input Enable = 0; Output Enable = 1; Open-drain = 0;

AUX_OUT_1 =1; AUX_OUT_2 = 0.

Note 5. GPIO configured: AUX_IN, Input Enable = 0; Output Enable = 1; Open-drain = 0;

AUX_OUT_1 = 0; AUX_OUT_2 = 1.

CS5535 Datasheet(PDF) 549 Page - National Semiconductor (TI)

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