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CS5535 Datasheet(PDF) 547 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 547 Page - National Semiconductor (TI) |
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547 / 555 page ![]() Revision 0.8 547 www.national.com Electrical Specifications (Continued) 6.3.12 UART and IR Signaling The UART support signals detailed in this sub-section use various types of buffers depending upon chip configuration. For a detailed explanation of buffer types, see Table 2-4 "Buffer Type Characteristics" on page 28. In this subsection, unless otherwise noted: • All timing specifications are specified under the oper- ating conditions listed in Table 6-3 on page 526 (i.e., VCORE and VCORE_VSB = All; VIO and VIO_VSB = All; TCASE = All). • No clock reference. Table 6-20. UART Timing Parameters Signal Parameter Min Max Units Comment/Condition UART1_TX (GPIO8) Async Output or Level NA NA ns Note 1. UART1_IR_TX (GPIO8) Async Output or Level NA NA ns Note 2. UART1_RX (GPIO9) Async Input NA NA ns Note 3. UART2_TX (GPIO4) Async Output or Level NA NA ns Note 1. UART2_RX (GPIO3) Async Input NA NA ns Note 3 Note 1. GPIO configured: AUX_IN and Input Enable = 0; Output Enable and AUX_OUT_1 = 1; Open-drain and AUX_OUT_2 = 0. Note 2. GPIO configured: AUX_IN and Input Enable = 0; Output Enable and AUX_OUT_2 = 1; Open-drain and AUX_OUT_1 = 0. Note 3. GPIO configured: AUX_IN and Input Enable = 1; Output Enable, AUX_OUT_1, and AUX_OUT_2 = 0. |
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