LTC1705 datasheet(13/28 Pages) LINER

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LTC1705

output, the duty cycle will be set at 1.5/5 • 100% or 30%

by the feedback loop. This will give roughly a 540ns on-

time for QT and a 1.26

µs on-time for QB.

This constant frequency operation brings with it a couple

of benefits. Inductor and capacitor values can be chosen

with a precise operating frequency in mind and the feed-

back loop components can be similarly tightly specified.

Noise generated by the circuit will always be in a known

frequency band with the 550kHz frequency designed to

leave the 455kHz IF band free of interference. Subharmonic

oscillation and slope compensation, common headaches

with constant frequency current mode switchers, are

absent in voltage mode designs like the LTC1705.

During the time that QT is on, its source (the SW pin) is at

VIN. VIN is also the power supply for the LTC1705. How-

ever, QT requires VIN+VGS(ON) at its gate to achieve mini-

mum RON. This presents a problem for the LTC1705—it

needs to generate a gate drive signal at TG higher than its

highest supply voltage. To accomplish this, the TG driver

runs from floating supplies, with its negative supply

attached to SW and its power supply at BOOST. This

allows it to slew up and down with the source of QT. In

combination with a simple external charge pump (Figure

2), this allows the LTC1705 to completely enhance the

gate of QT without requiring an additional, higher supply

voltage.

The two channels of the LTC1705 run from a common

clock, with the phasing chosen to be 180

° from the core

side to the I/O side. This has the effect of doubling the

frequency of the switching pulses seen by the input

bypass capacitor, lowering the RMS current seen by the

capacitor and reducing the value required.

Feedback Amplifier

Each side of the LTC1705 senses the output voltage at

VOUT with an internal feedback op amp (see Block Dia-

gram). This is a real op amp with a low impedance output,

85dB open-loop gain and 20MHz gain bandwidth product.

The positive input is connected internally to an 800mV

reference, while the negative input is connected to the FB

pin. The output is connected to COMP, which is in turn

connected to the soft-start circuitry and from there to the

PWM generator.

Unlike many regulators that use a resistor divider con-

nected to a high impedance feedback input, the LTC1705

is designed to use an inverting summing amplifier topol-

ogy with the FB pin configured as a virtual ground. This

allows flexibility in choosing pole and zero locations not

available with simple gm configurations. In particular, it

allows the use of “Type 3” compensation, which provides

a phase boost at the LC pole frequency and significantly

improves loop phase margin (see Figure 3). Note that the

core side of the LTC1705 includes R1 and RB internally as

part of the VID DAC circuitry.

APPLICATIO S I FOR ATIO

PGND

LTC1705

CIN

COUT

1705 F01

VOUT

VIN

CCP

DCP

BOOST

PGND

PVCC

LTC1705

CIN

COUT

1705 F02

VOUT

VIN

–

0.8V

VOUT

LTC1705

COMP

1705 F03

Figure 2. Floating TG Driver Supply

Figure 1. Synchronous Buck Architecture

Figure 3. "Type 3" Feedback Loop (I/O Channel)

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