UPD6P8 datasheet(41/101 Pages) RENESAS

41 / 101 page

µPD6P8, 6P8A, 6P8B

Data Sheet U17848EJ5V0DS

7. RESET

A system reset is effected by the following causes:

• When the POC circuit has detected low power-supply voltage

• When the operand value is illegal or does not satisfy the precondition when the HALT instruction is executed

• When the accumulator is 0H when the RLZ instruction is executed

• When stack pointer overflows or underflows

Table 7-1. Hardware Statuses After Reset

Hardware

• Reset by On-Chip POC Circuit During Operation

• Reset by the On-Chip POC Circuit During

• Reset by Other FactorsNote 1

Standby Mode

000H

SP (1 bit)

Data

R0 = DP

000H

memory

R1 to RF

Undefined

Accumulator (A)

Undefined

Status flag (F)

Carry flag (CY)

Timer (10 bits)

000H

Port register

FFH

µPD6P8, 6P8A: ×××× 11×1BNote 2, µPD6P8B: ×××× 11×0BNote 2

Control register P3

0000

×000BNote 3

26H

Notes 1. The following resets are available.

• Reset when executing the HALT instruction (when the operand value is illegal or does not satisfy

the precondition)

• Reset when executing the RLZ instruction (when A = 0)

• Reset by stack pointer’s overflow or underflow

×: Refers to the value by the KI or S2 pin status.

In order to prevent malfunction, be sure to input a low level to one or more of pins KI0 to KI3 when

POC is released by supply voltage rising (Can be left open. When open, leave the pull-down resistor

connected).

×: Refers to the value based on a decrease of power supply voltage (0 when VDD ≤ VID).

Remark VID: RAM retention detection voltage

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