MCP1501 datasheet(19/39 Pages) MICROCHIP

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DS20005474G-page 19

MCP1501

5.0

APPLICATION CIRCUITS

5.1

Application Tips

5.1.1

BASIC APPLICATION CIRCUIT

Figure 5-1 illustrates a basic circuit configuration of the

MCP1501.

FIGURE 5-1:

Basic Circuit Configuration.

An output capacitor is not required for stability of the

voltage reference, but may be optionally added to

provide noise filtering or act as a charge-reservoir for

switching loads, e.g., successive approximation

shown, the input voltage is connected to the device at

the VIN input, with an optional 2.2 μf ceramic capacitor.

This capacitor would be required if the input voltage

has excessive noise. A 2.2 μf capacitor would reject

input voltage noise at approximately 1 to 2 MHz. Noise

below this frequency will be amply rejected by the input

voltage rejection of the voltage reference. Noise at

frequencies above 2 MHz will be beyond the bandwidth

of the voltage reference and, consequently, not

transmitted from the input pin through the device to the

output.

If the noise at the output of the voltage references is too

high for the particular application, it can be easily fil-

tered with an external RC filter and op-amp buffer (see

Figure 5-2).

FIGURE 5-2:

Output Noise-Reducing

Filter.

The RC filter values are selected for a desired cutoff

frequency, as shown in Equation 5-1.

EQUATION 5-1:

The values that are shown in Figure 5-2 (10 kΩ

 and

1 μF) will create a first-order, low-pass filter at the out-

put of the amplifier. The cutoff frequency of this filter is

15.9 Hz, and the attenuation slope is 20 dB/decade.

The MCP6286 amplifier isolates the loading of this low-

pass filter from the remainder of the application circuit.

This amplifier also provides additional drive, with a

faster response time than the voltage reference.

5.1.2

LOAD CAPACITOR

The maximum capacitive load without series resistance

is 10nF. However, larger capacitors may be

implemented if a resistor is used in series with a larger

load capacitor. Refer to Figure 3-29, Figure 3-30 and

Figure 3-31 for the transient response with the series

resistor and capacitive load.

5.1.3

PRINTED CIRCUIT BOARD LAYOUT

CONSIDERATIONS

Mechanical stress due to Printed Circuit Board (PCB)

mounting can cause the output voltage to shift from its

initial value. Devices in the SOT-23-6 package are gen-

erally more prone to assembly stress than devices in

the WDFN package. To reduce stress-related output

voltage shifts, mount the reference on low-stress areas

of the PCB (i.e., away from PCB edges, screw holes

and large components).

VDD

SHDN

GND

SOIC-8/DFN-8

GND

FEEDBACK

OUT

GND

0.1

– 2.2 μF

1.65

– 5.5V

OUT

Output

of V

REF

 R1 C1



-----------------------------

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