UPD67B datasheet(20/73 Pages) RENESAS

20 / 73 page

µPD67B, 68B

Data Sheet U16792EJ1V1DS

3.3.1 RAM retention flag (bit 3 of P3)

The RAM retention flag indicates whether the supply voltage has fallen below the level at which the contents

of the RAM are lost while the battery is being exchanged or when the battery voltage has dropped.

This flag is at bit 3 of control register 0 (P3).

It is cleared to 0 if the supply voltage drops below the RAM retention detection voltage (approx. 1.5 V TYP.).

If this flag is 0, it can be judged that the RAM contents have been lost or that power has just been applied. This

flag can be used to initialize the RAM via software. After initializing the RAM and writing the necessary data to it,

set this RAM retention flag to 1 by software. At this time, 1 means that data has been set to the RAM.

Figure 3-2. Supply Voltage Transition and Detection Voltage

(1) If the supply voltage rises after the battery has been set, and exceeds VPOC (POC detection voltage),

reset is cleared. Because the supply voltage rises from 0 V, which is lower than VID (RAM retention

detection voltage), the RAM retention flag remains in the initial status 0.

(2) The supply voltage has now risen to the level at which the device can operate. Write the necessary data

to the RAM and set the RAM retention flag to 1.

(3) The device is reset if the supply voltage drops below VPOC. At point (A) in the figure, the voltage is lower

than VID. Consequently, the RAM retention flag is cleared to 0.

(4) If the RAM retention flag is checked by software after reset has been cleared, it is 0. This means that

the contents of the RAM may have been lost. If this case, initialize the RAM by software.

Cautions 1. The software developed for the

µPD67, 67A, 68, 68A, and 69 (using the RAM retention flag)

can be used for the

µPD67B and 68B as is.

2. Unlike the

µPD67, 67A, 68, 68A, and 69, the RAM retention detection voltage of the µPD67B

and 68B is the same as the POC detection voltage. When software is newly developed,

it is not necessary to use the RAM retention flag if only the RAM is initialized by reset.

VDD

VPOC/VID

0 V

RAM retention flag

(A)

(4)

(3)

(2)

Set to 1

Flag contents

are read

(1)

POC detection voltage/

RAM retention detection voltage

VPOC = VID = 1.5 V (TYP.)

UPD67B Datasheet(PDF) 20 Page - Renesas Technology Corp

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