VITESSE

SEMICONDUCTOR CORPORATION

Datasheet

VSC835

2.5 Gbits/sec

34x34 Crosspoint Switch with Signal Detection

Page 2

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

7/24/00

G52270-0, Rev. 4.1

Figure 1: Detailed Block Diagram

Functional Description

Data Paths

All input data must be differential and biased to PECL levels. On-chip terminations are provided, with a

Data outputs are provided through differential current switches with on-chip terminations that produce a

PECL level output swing. The drive level of the output circuit is designed to produce standard PECL levels

when terminated in 50 ohms to 2.0 volts. Other termination voltages are possible, such as to VCC or 1.3 volts,

but the voltage level of the output will be shifted from its nominal value. The common-mode voltage of the out-

put swing can be adjusted using the VCOM pins. The adjustment range is not calibrated, but typically allows for

+/- 200mV of adjustment in common-mode voltage. The VCOM pin self-biases to a nominal value when left

unconnected.

Output channels can be powered off in pairs if fewer than 34 outputs are required. By connecting the VEE

pin associated with a given pair of outputs to VCC, the output pairs will pull to VCC and chip power will be

reduced by approximately 300mW per pair.

A,AN[33:0]

Control interface

DATA[5:0], ADDR[5:0]

ALE, CSB, WRB, RDB

INTB, MONCLK, CONFIG

Y,YN[33:0]

34

34 x 34

switch core

Program memory