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MP86957 Datasheet(PDF) 3 Page - Monolithic Power Systems |
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MP86957 Datasheet(HTML) 3 Page - Monolithic Power Systems |
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3 / 16 page ![]() MP86957 – INTELLI-PHASETM SOLUTION IN 5MMX6MM LGA MP86957 Rev. 1.1 www.MonolithicPower.com 3 7/10/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name Description 1, 6, 31, 37, 39, 41 NC No connection. 2 AGND Analog ground. 3 VDD Supply voltage for internal circuitry. Connect to the VDRV pin through a 2.2Ω resistor and decouple with a 1µF capacitor to AGND. Connect AGND and PGND at the VDD capacitor. 4 VDRV Driver voltage. Connect to 3.3V supply and decouple with a 1µF to 4.7µF ceramic capacitor. 5, 7, 8, 9, 20, 21, 22, 23, 24, 40 PGND Power ground. 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 SW Phase node. 25, 26, 27, 28, 29, 30 VIN Input supply voltage. Place input ceramic capacitors (CIN) close to the device to support the switching current with minimal parasitic inductance. 32 PHASE Switching node for bootstrap capacitor connection. PHASE pin is connected to SW internally. 33 BST Bootstrap. Requires a 0.1µF to 0.22 µF capacitor to drive the power switch’s gate above the supply voltage. Connect the capacitor between PHASE and BST to form a floating supply across the power switch driver. 34 PWM Pulse-width modulation input. Leave PWM floating or drive to mid-state to put SW in high-impedance state. 35 EN Enable. Pull low to disable the device and place SW in a high-impedance state. 36 TOUT/FLT Single-pin temperature sense and fault reporting. When a fault occurs, the pin is pulled up to the VDD voltage. 38 IOUT Current sense output. Use an external resistor to adjust the voltage proportional to the inductor current. |
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