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MP86957 Datasheet(PDF) 5 Page - Monolithic Power Systems

Part # MP86957
Description  Intelli-PhaseTM Solution (Integrated HS/LS-FETs and Driver) in 5mmx6mm LGA
PDF  16 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP86957 Datasheet(HTML) 5 Page - Monolithic Power Systems

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MP86957
– INTELLI-PHASETM SOLUTION IN 5MMX6MM LGA
MP86957 Rev. 1.1
www.MonolithicPower.com
5
7/10/2020
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
ELECTRICAL CHARACTERISTICS
VIN = 12V, VDRV = VDD = EN = 3.3V; TA = 25°C for typical value and TJ = -40°C to +125°C for max
and min values, unless otherwise noted.
Parameter
Symbol
Condition
Min
Typ
Max
Units
IIN shutdown
EN = low
90
180
μA
VIN under-voltage lockout threshold
rising
2.5
3.0
V
VIN under-voltage lockout threshold
hysteresis
450
mV
IVDRV quiescent current
PWM = low
250
350
μA
IVDD quiescent current
PWM = low
3
mA
VDD voltage UVLO rising
2.75
2.95
V
VDD voltage UVLO hysteresis
300
mV
High-side current limit (4)
ILIM_FLT
Cycle-by-cycle up to 8
cycles
95
A
High-side current limit tolerance (4)
-15%
+15%
Low-side current limit (4)
Negative current limit,
cycle-by-cycle, no fault
report
-40
A
Low-side current limit tolerance (4)
-15%
+15%
Negative current limit low-side off
time (4)
200
ns
High-side current limit fault flag
counter (4)
8
times
High-side current limit fault flag
clear counter (4)
4
times
Dead time at SW rising (4)
2
ns
Dead time at SW falling (4)
Positive inductor
current
6
ns
Negative inductor
current
28
ns
EN input high threshold voltage
2.30
V
EN input low threshold voltage
0.8
V
PWM high to SW rising delay (4)
tRising
20
ns
PWM low to SW falling delay (4)
tFalling
20
ns
PWM tri-state to SW Hi-Z delay (4)
tLT
40
ns
tTL
30
ns
tHT
40
ns
tTH
30
ns
Minimum PWM pulse width (4)
30
ns
IOUT sense gain accuracy (4)
20A ≤ ISW ≤ 70A
-2
0
+2
%
IOUT sense gain
GIOUT
5
μA/A



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