7

VP7615

89

Out

SCLOA

Serial Clock Out Port A - This output drives the level on the SCLI input when the

CamPort™ A is selected. When the CamPort™ B is selected this output is driven high.

This is not an open-drain output.

90

Out

SCLOB

Serial Clock Out Port B - This output drives the level on the SCLI input when the

CamPort™ B is selected. When the CamPort™ A is selected this output is driven high.

This is not an open-drain output.

99

Out

GPIO7

General Purpose I/O Bit 7 - This bus represents eight general purpose I/O pins. Each

bit may programmed to be an input or an ouput; on reset, all GPIO pins default to high

impedance (tri-state) inputs.

98

Out

GPIO6

General Purpose I/O Bit 6

97

Out

GPIO5

General Purpose I/O Bit 5

96

Out

GPIO4

General Purpose I/O Bit 4

95

Out

GPIO3

General Purpose I/O Bit 3

94

Out

GPIO2

General Purpose I/O Bit 2

93

Out

GPIO1

General Purpose I/O Bit 1

92

Out

GPIO0

General Purpose I/O Bit 0

52

In

TST0

Test Pin - This pin should be tied low.

53

In

TST1

Test Pin - This pin should be tied low.

61

In

TST2

Test Pin - This pin should be tied low.

62

In

TST3

Test Pin - This pin should be tied low.

63

In

TST4

Test Pin - This pin should be tied low.

71

In

TSTOE

Test Output Enable - This pin should be tied high.

Out

TOUT

Test Outputs - These pins should be unconnected.

In

GND

Power

In

VDD

Power

64, 65, 66,

67, 70, 72,

73, 74, 77,

78, 79, 80,

81,

1, 7, 19,

25, 32, 51,

57, 69, 75,

82,

8, 18, 26,

33, 50, 58,

68, 76, 83,

100