UPD9993 datasheet(20/102 Pages) RENESAS

20 / 102 page

µ PD9993

Data Sheet S17306EJ2V0DS

2. GENERAL DESCRIPTION

2.1 Block Diagram

Figure 2-1. Block Diagram

Sound

generator

Lch

D7 to D1

RD_B/SPIMODE

WR_B/SCLK

CS_B/SCS

AGND

LED

Rch

Lch

Analog block

(AVDD, AVDD_P)

Digital block

(DVDD, EVDD)

CLKIN

INT_SG_B

A0/Data,TXD

VIB

LED

VREF

IREF

AVDD

LINEOUT_L

LINEOUT_R

Rch

RESET_B

Vibrator

ASIO

PLL1

PLL2

DAC

A1/RXD

D0/SERINIT

INT_DSP_B

MP3/AAC

decoder

(DSP)

Lch

Rch

AST

(1) PLL1, PLL2 (CLKIN pin)

Clock input in the range from 2.688 to 26 MHz is supported.

In this block, when a clock with a frequency in this range is input, it is multiplied by the PLL to generate the

fixed frequency clock that is required internally. PLL1 generates the clock signals required by all blocks except

for the sound generator block and MP3/AAC decoder block, and PLL2 generates the clock signal for the sound

generator block and MP3/AAC decoder block. After activation, normal operation begins after at least 5 ms

have elapsed.

(2) CPU interface

This connects to the host CPU via an 8-bit parallel interface or 3/4-wire serial peripheral interface (SPI).

(3) Vibrator, LED control output port

This is an output port for the LED and vibrator.

(4) PCM sound generator block

A PCM sound generator for generation of up to 64 simultaneous tones is on chip, along with a sequencer. The

sampling frequency is 32 kHz. The playback function for ADPCM is also on chip. The sampling frequency

options are 8 kHz × 4 channels, 16 kHz × 2 channels, and 32 kHz × 1 channel.

UPD9993 Datasheet(PDF) 20 Page - Renesas Technology Corp

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