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AD8339 Datasheet(PDF) 4 Page - Analog Devices |
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AD8339 Datasheet(HTML) 4 Page - Analog Devices |
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4 / 15 page  AD8339 Preliminary Technical Data Rev. PrA | Page 4 of 15 PHASE ROTATION PERFORMANCE One CH is reference, others are stepped Phase Increment 16 Phase Steps per Channel 22.5 ° Quadrature Phase Error Ix to Qx; all phases, 1 σ ±1 ° I/Q Amplitude Imbalance Ix to Qx; all phases, 1 σ 0.25 dB Channel-to-Channel Matching Phase Match I-to-I and Q-to-Q; -40 °C < T A < 85 °C ±1 ° Ampl. Match I-to-I and Q-to-Q; -40 °C < T A < 85 °C ±0.5 dB LOGIC INTERFACES Pins SDI,CSB,SCLK, RSTS,RSET Logic Level High 1.5 V Logic Level Low 0.9 V Bias Current Logic High (pulled to +5V) 0.5 μA Logic Low (pulled to GND) 0 μA Input Resistance 4 M Ω LO Divider RSET Setup Time RSET rising edge to 4LOP-4LON (Differential) rising edge 5 ns LO Divider RSET High Pulse Width 20 ns LO Divider RSET Setup Time RSET falling edge prior to 4LOP-4LON (Differential) rising edge 5 ns Phase Response Time Measured from CSB going high TBD μs Enable Response Time Measured from CSB going high (with 0.1 μF cap on pin LODC) 15 μs Output Pin SDO Logic Level High Loaded with 5 pF and next SDI input 1.7 1.9 V Logic Level Low Loaded with 5 pF and next SDI input 0.2 0.5 V SPI TIMING CHARACTERISTICS Pins SDI,SDO,CSB,SCLK, RSTS SCLK Frequency fCLK 10 MHz CSB to SCLK Setup Time T1 TBD ns SCLK High Pulse Width T2 TBD ns SCLK Low Pulse Width T3 TBD ns Data Access Time after SCLK Falling Edge T4 TBD ns Data Setup Time Prior to SCLK Rising Edge T5 TBD ns Data Hold Time after SCLK Rising Edge T6 TBD ns CSB High Pulse Width T7 TBD ns SCLK Fall to CSB Fall Hold Time T8 TBD ns SCLK Fall to CSB Rise Hold Time T9 TBD POWER SUPPLY Pins VPOS,VNEG Supply Voltage ±4.5 ±5 ±5.5 V Quiescent Current VPOS, all phase bits = 0 37.5 mA VNEG, all phase bits = 0 -21 mA Over Temperature -40 °C < T A < 85 °C TBD TBD mA Quiescent Power Per Channel, all phase bits = 0 73 mW Per Channel max (depends on phase bits) TBD mW Disable Current All Channels Disabled; SPI stays on 2.6 mA PSRR VPOS to Ix/Qx outputs (meas. @ AD8021 output) TBD dB VNEG to Ix/Qx outputs (meas. @ AD8021 output) TBD dB |
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