Preliminary

Technical Data

AD8339

Rev. PrA | Page 13 of 15

In a real application, the phase difference depends on the

element spacing, λ (wavelength), speed of sound, angle of

incidence, and other factors. The signals ES1 and ES2 are

amplified 19 dB by the low-noise amplifiers in the AD8332; for

lower performance portable ultrasound applications, the

combination of the AD8335 and the AD8339 result in the

lowest power per channel. For optimum signal-to-noise

performance, the output of the LNA is applied directly to the

input of the AD8339. In order to sum the signals ES1 and ES2,

ES2 is shifted 45° relative to ES1 by setting the phase code in

Channel 2 to 0010. The phase aligned current signals at the

output of the AD8333 are summed in an I-to-V converter to

provide the combined output signal with a theoretical

improvement in dynamic range of 3 dB for the sum of two

channels.

SERIAL INTERFACE

The AD8339 contains a 4-wire SPI compatible digital interface

(SDI, SCLK, CSB, and SDO). The interface is comprised of a 20-

bit shift register plus a latch. The shift register needs to be loaded

MSB first. The data allows control over each channel’s phases,

plus the last four bits shifted into the register determine the

and timing diagram of the serial interface. The shift direction is

to the “right” with MSB first. As soon CSB goes low, the data in

the latch is protected and new data can be loaded into the shift

register.

If only one AD8339 needs to be programmed, then only 20 bits

need to be shifted into the part before CSB goes high. As soon

as CSB goes high, the data loaded into the shift register will be

transferred to the latch. Depending on the data loaded the

corresponding channels will be enabled, and the phases on each

look when two AD8339s have their data loaded.

ENBL Bits

If all four ENBL bits are set to ‘0’, then only the SPI port is

powered up. This feature allows for very low power

consumption (about 13 mW per AD8339 or 3.25 mW per

channel) when the CW Doppler function is not needed. Since

the SPI port stays alive even when the rest of the chip is

powered down, the part can be awakened again by simply

programming the port. As soon as the CSB signal goes high, the

part turns on again. It should be pointed out that this will take a

fair amount of time because of the external capacitor on the

LODC pin. It will take about 10-20 μs with the recommended

0.1 μF decoupling cap. The decoupling cap on this pin is

intended to reduce bias noise contribution in the LO divider

chain. The user can experiment with the value of this

decoupling capacitor to see what the smallest value can be

without any dynamic range degradation within the frequency

band of interest.

The SPI also has an additional pin that can be used in a test

mode, or as a quick way to reset the SPI and de-power the chip.

All bits in both the shift register and the latch can be reset to ‘0’

when pin RSTS is pulled above about 1.2 V. For quick testing

without the need to program the SPI, the voltage on the RSTS

pin should be first pulled high and then pulled to -1.4 V; this

enables all four channels in the (I=1,Q=0) state (all phase bits

are 0000).