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ADM487EARZ Datasheet(PDF) 5 Page - Analog Devices

Part # ADM487EARZ
Description  5 V, 짹15 kV ESD Protected Half-Duplex, RS-485/RS-422 Transceivers
PDF  16 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADM487EARZ Datasheet(HTML) 5 Page - Analog Devices

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ADM485E/ADM487E/ADM1487E
Rev. 0 | Page 5 of 16
VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 4. ADM487E
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DRIVER
Input to Output
tDPLH
250
800
2000
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
tDPHL
250
800
2000
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
Output Skew to Output
tSKEW
250
20
800
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
Rise/Fall Time
tDR, tDF
250
2000
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
Enable Time to High Level
tDZH
250
2000
ns
CRL = 100 pF, S2 closed (see Figure 21)
Enable Time to Low Level
tDZL
2000
ns
CRL = 100 pF, S1 closed (see Figure 22)
Disable Time from Low Level
tDLZ
300
3000
ns
CRL = 15 pF, S1 closed (see Figure 22)
Disable Time from High Level
tDHZ
300
3000
ns
CRL = 15 pF, S2 closed (see Figure 21)
RECEIVER
Input to Output
tRPLH
250
2000
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
tRPHL
250
2000
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
|tPLH − tPHL| Differential Receiver Skew
tSKEW
100
ns
CRL = 15 pF, S1 closed
(see Figure 23 and Figure 24)
Enable Time to Low Level
tRZL
25
50
ns
CRL = 15 pF, S2 closed (see Figure 25)
Enable Time to High Level
tRZL
25
50
ns
CRL = 15 pF, S1 closed (see Figure 25)
Disable Time from Low Level
tRLZ
25
50
ns
CRL = 15 pF, S2 closed (see Figure 25)
Disable Time from High Level
tRHZ
25
50
ns
tPLH, tPHL < 50% of data period
Maximum Data Rate
fMAX
250
kbps
Time to Shutdown1
tDZH(SHDN)
50
200
600
ns
CL = 100 pF, S2 closed (see Figure 21)
Driver Enable from Shutdown to Output High
tDZL(SHDN)
5000
ns
CL = 100 pF, S1 closed (see Figure 22)
Driver Enable from Shutdown to Output Low
tRZL(SHDN)
5000
ns
CL = 15 pF, S2 closed (see Figure 25)
Receiver Enable from Shutdown to Output High
tRZH(SHDN)
5000
ns
CL = 15 pF, S1 closed (see Figure 25)
1 The ADM487E is put into shutdown mode by bringing the RE high and the DE low. If the inputs are in this state for less than 50 ns, the parts are guaranteed not to
enter shutdown. If the inputs are in this state for at least 600 ns, the ADM487E is guaranteed to enter shutdown.



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