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UPD17062 Datasheet(PDF) 181 Page - Renesas Technology Corp |
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UPD17062 Datasheet(HTML) 181 Page - Renesas Technology Corp |
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181 / 298 page  179 µPD17062 Fig. 14-5 Power-on Reset and VDD (a) During normal operation (including halt state) (b) At clock-stop (c) When VDD rises from 0 V 5 V 0 V “H” Normal operation Device operation stopped XOUT VDD CE Power-on clear signal Power-on clear release Oscillation start Power-on reset Program starts from address 0 Halt state 50 ms Power-on clear voltage 3.5 V 5 V Clock-stop Device operation stopped XOUT VDD CE Power-on clear signal Power-on clear release Oscillation start Power-on reset Program starts from address 0 Halt state 50 ms 2.2 V Power-on clear voltage 3.5 V STOP 0000B Normal operation “L” 5 V 0 V Device operation stopped XOUT VDD CE Power-on clear signal Power-on clear release Oscillation start Power-on reset Program starts from address 0 Halt state 50 ms 3.5 V Power-on clear voltage “L” |
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