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UPD17062 Datasheet(PDF) 183 Page - Renesas Technology Corp |
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UPD17062 Datasheet(HTML) 183 Page - Renesas Technology Corp |
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183 / 298 page ![]() 181 µPD17062 Fig. 14-6 Relationship Between Power-on Reset and CE Reset (a) When VDD and CE pin raised simultaneously (b) When CE pin raised in halt state (c) When CE pin raised after power-on reset 5 V 0 V Opera- tion stopped VDD CE Power-on reset Program start Power-on clear voltage 3.5 V Halt state 50ms Normal operation Timer carry FF set pulse 5 V 0 V VDD CE Power-on reset Program start Power-on clear voltage 3.5 V Halt state 50 ms Normal operation Timer carry FF set pulse Opera- tion stopped 0 V VDD CE Timer carry FF set pulse Power-on reset Program start Power-on clear voltage 3.5 V Halt state 50 ms Normal operation CE reset Program start Opera- tion stopped 5 V |
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