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UPD17062 Datasheet(PDF) 182 Page - Renesas Technology Corp |
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UPD17062 Datasheet(HTML) 182 Page - Renesas Technology Corp |
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182 / 298 page  180 µPD17062 14.5 RELATIONSHIP BETWEEN CE RESET AND POWER-ON RESET When supply voltage is first turned on, power-on reset and CE reset may be applied simultaneously. Sections 14.5.1 through 14.5.3 describe this reset operation. Section 14.5.4 describes the cautions when supply voltage rises. 14.5.1 When VDD Pin and CE Pin Rise Simultaneously Fig. 14-6 (a) shows the reset operation. Power-on reset starts the program from address 0000H. 14.5.2 When CE Pin Raised in Forced Halt State Caused by Power-on Reset. Fig. 14-6 (b) shows the reset operation. Power-on reset starts the program from address 0000H, as in Section 14.5.1. 14.5.3 When CE Pin Raised after Power-on Reset Fig. 14-6 (c) shows the reset operation. Power-on reset starts the program from address 0000H. CE reset restarts the program from address 0000H at the rising edge of the next timer carry FF set signal. |
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