UPD30102 datasheet(23/114 Pages) RENESAS

23 / 114 page

µPD30102

Preliminary Data Sheet

2. INTERNAL BLOCKS

For the internal block configuration, see the figure in P. 4.

2.1 VR4100 CPU Core

(1) CPU

The CPU processes integer instructions and consists of 64-bit register files, a 64-bit integer data bus, and

a sum-of-products operation unit.

(2) Coprocessor 0 (CP0)

The CP0 has a memory management unit (MMU) and an exception processing function. The MMU translates

addresses and checks whether an access is made between different types (user, supervisor, or kernel) of

memory segments. Translation of virtual addresses to physical addresses is performed by TLB (high-speed

translation lookaside buffer).

(3) Instruction cache

The instruction cache is 4-Kbyte capacity, consisting of direct mapping, virtual index, and physical tag type.

(4) Data cache

The data cache is 1-Kbyte capacity, consisting of direct mapping, virtual index, physical tag, and write back

type.

(5) CPU bus interface

The CPU bus interface controls data transfer between the VR4100 CPU core and BCU, one of the peripheral

units. As the bus interface for the VR4100 CPU core, two 32-bit address/data multiplexed buses each for

input and output, clock signals, and interrupt control signals are used.

2.2 Clock Generator

The following clock inputs are oscillated to generate and supply clocks to internal units.

• 32.768-kHz clock for RTC. The 32.768-kHz clock generated by the crystal resonator is oscillated by the internal

oscillator, and supplied to the RTC unit.

• 18.432-MHz clock for serial interface, touch panel interface, and reference operating clock of the VR4102. The

18.432-MHz clock generated by the crystal resonator is oscillated by the internal oscillator, multiplied by PLL

(phase-locked loop), to generate the pipeline clock (PClock). The internal bus clock (TClock) is generated

from PClock.

2.3 BCU (Bus Control Unit)

The BCU internally transfers data with the VR4100 CPU core via SysAD bus (internal). It also controls the LCD

controller, DRAM, ROM (flash memory or mask ROM), and PCMCIA controller connected to the system bus, and

transfers data with the above devices via ADD and DATA buses.

2.4 RTC (Real-time Clock)

The RTC has a precise counter that operates with a 32.768-kHz clock supplied from the clock generator. It also has

several counters and compare registers for various interrupts.

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