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Rev.0.0

Dual-ChannelIsolatedGateDriver

BTD21520x

9.5.4 BTD21520EDeadTime

A dead time elapses before OUT1 or OUT2 goes high, so as to prevent the high and low side MOSFET shoot-through.

Figure10.LogicrelationshipbetweeninputandoutputsignalsofBTD21520E

9.6ProtectionFunction

9.6.1UVLO

There is an internal undervoltage lock-out (UVLO) on the power circuit function area between VDDx and VEE pins

of two out-puts.When the voltage of VDD is below the undervoltage recovery threshold before starting, or be-

low the undervoltage protection threshold after starting, the output will remain low regardless of the input state.

When the output of the driver is in powered-off or undervoltage state, its output is clamped to the low level by the ac-

tive clamping circuit, as shown in the figure below.At this time, the PMOS of the high side is blocked and high imped-

ance, and the NMOS gate of the low side is connected to the output of the driver by the resistor RCLAMP.In the absence of

bias voltage, the output is effectively clamped to the threshold voltage of the low-side NMOS device, typically around 1.5V

(see Figure 11-1).

Figure11-1 SimplifiedRepresentationofActivePulldownFeature

The VDDx undervoltage protection has a VVDD_HYS feature that prevents vibration in the presence of noise

from the power supply to ground. This also allows the device to accept a small decrease in bias volt-

age when the device starts to turn on/off and the operating current consumption increases abruptly.

Like the VDDx, there is also an undervoltage lock-out (UVLO) integrated on the primary side of the VCC.When the bias

voltage is applied to the VCC terminal and the voltage is lower than the undervoltage turn-on threshold, the device will

not be activated.After the activation of the device, if the VCC voltage continuously decreases to the undervoltage turn-

off threshold, the signal will stop transmission.Like the undervoltage lockout of VDD, the undervoltage lockout of VCC

also has hysteresis feature.

DT

OUT2

OUT1

PWM

VEE

VDD

Output

Control

RCLAMP

OUT

RCLAMP is activated

During UVLO