SST25VF040 datasheet(4/23 Pages) SST

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EOL Product Data Sheet

2 Mbit / 4 Mbit SPI Serial Flash

SST25VF040

S71231(04)-00-000

10/06

PRODUCT IDENTIFICATION

MEMORY ORGANIZATION

The SST25VF040 SuperFlash memory array is organized

in 4 KByte sectors with 32 KByte overlay blocks.

DEVICE OPERATION

The SST25VF040 is accessed through the SPI (Serial

Peripheral Interface) bus compatible protocol. The SPI bus

consist of four control lines; Chip Enable (CE#) is used to

select the device, and data is accessed through the Serial

Data Input (SI), Serial Data Output (SO), and Serial Clock

(SCK).

The SST25VF040 supports both Mode 0 (0,0) and Mode 3

(1,1) of SPI bus operations. The difference between the

two modes, as shown in Figure 3, is the state of the SCK

signal when the bus master is in Stand-by mode and no

data is being transferred. The SCK signal is low for Mode 0

and SCK signal is high for Mode 3. For both modes, the

Serial Data In (SI) is sampled at the rising edge of the SCK

clock signal and the Serial Data Output (SO) is driven after

the falling edge of the SCK clock signal.

FIGURE 3: SPI Protocol

TABLE

2: Product Identification

Address

Data

Manufacturer’s ID

00000H

BFH

Device ID

SST25VF040

00001H

44H

T2.0 1231(04)

1231 F02.1

MODE 3

SCK

CE#

MODE 3

DON'T CARE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0

HIGH IMPEDANCE

MSB

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