SST25VF040 datasheet(13/23 Pages) SST

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EOL Product Data Sheet

2 Mbit / 4 Mbit SPI Serial Flash

SST25VF040

S71231(04)-00-000

10/06

Write-Enable (WREN)

The Write-Enable (WREN) instruction sets the Write-

Enable-Latch bit to 1 allowing Write operations to occur.

The WREN instruction must be executed prior to any Write

(Program/Erase) operation. CE# must be driven high

before the WREN instruction is executed.

FIGURE 12: Write Enable (WREN) Sequence

Write-Disable (WRDI)

The Write-Disable (WRDI) instruction resets the Write-

Enable-Latch bit and AAI bit to 0 disabling any new Write

operations from occurring. CE# must be driven high before

the WRDI instruction is executed.

FIGURE 13: Write Disable (WRDI) Sequence

Enable-Write-Status-Register (EWSR)

The Enable-Write-Status-Register (EWSR) instruction

arms the Write-Status-Register (WRSR) instruction and

opens the status register for alteration. The Enable-Write-

Status-Register instruction does not have any effect and

will be wasted, if it is not followed immediately by the Write-

Status-Register (WRSR) instruction. CE# must be driven

low before the EWSR instruction is entered and must be

driven high before the EWSR instruction is executed.

CE#

SCK

01 2 3 4 5 6 7

HIGH IMPEDANCE

MODE 0

MODE 3

1231 F11.1

MSB

CE#

SCK

01 2 3 4 5 6 7

HIGH IMPEDANCE

MODE 0

MODE 3

1231 F12.1

MSB

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