TMS320VC549 datasheet(49/63 Pages) TI

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TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078G − SEPTEMBER 1998 − REVISED OCTOBER 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

serial-port receive timing in TDM mode

timing requirements over recommended ranges of supply voltage and operating free-air

temperature [H = 0.5tc(CO)] (see Figure 27)

549-80

549-100

549-120

UNIT

MIN

MAX

tc(SCK)

Cycle time, serial-port clock

16H

†

tf(SCK)

Fall time, serial-port clock

tr(SCK)

Rise time, serial-port clock

tw(SCK)

Pulse duration, serial-port clock low/high

tsu(TD-TCH)

Setup time, TDAT/TADD before TCLK rising edge

th(TCH-TD)

Hold time, TDAT/TADD after TCLK rising edge

tsu(TF-TCH)

Setup time, TFRM before TCLK rising edge‡

th(TCH-TF)

Hold time, TFRM after TCLK rising edge‡

† The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching infinity. It is characterized approaching an input frequency

of 0 Hz but tested at a much higher frequency to minimize test time.

‡ TFRM timing and waveforms shown in Figure 27 are for external TFRM. TFRM can also be configured as internal. The TFRM internal case is

illustrated in the transmit timing diagram in Figure 28.

TMS320VC549 Datasheet(PDF) 49 Page - Texas Instruments

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