TMS320VC549 datasheet(19/63 Pages) TI

19 / 63 page

TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078G − SEPTEMBER 1998 − REVISED OCTOBER 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

multiply-by-N clock option − PLL enabled (continued)

timing requirements for multiply-by-N clock option − PLL enabled (see Figure 4)

549-80

549-100

549-120

UNIT

MIN

MAX

MIN

MAX

UNIT

Integer PLL multiplier N (N = 1−15)

20†

200

20†

200

tc(CI)

Cycle time, X2/CLKIN

PLL multiplier N = x.5

20†

100

20†

100

tc(CI)

Cycle time, X2/CLKIN

PLL multiplier N = x.25, x.75

20†

tf(CI)

Fall time, X2/CLKIN

tr(CI)

Rise time, X2/CLKIN

tw(CIL)

Pulse duration, X2/CLKIN low

tw(CIH) Pulse duration, X2/CLKIN high

† Note that for all values of tc(CI), the minimum tc(CO) period must not be exceeded.

tc(CO)

tc(CI)

tw(COH)

tf(CO)

tr(CO)

tf(CI)

X2/CLKIN

CLKOUT

td(CIH-CO)

tw(COL)

tr(CI)

Unstable

tw(CIH)

tw(CIL)

Figure 4. External Multiply-by-One Clock Timing

TMS320VC549 Datasheet(PDF) 19 Page - Texas Instruments

TMS320VC549 Datasheet(HTML) 19 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Datasheet Download

Link URL