RT6220 datasheet(14/20 Pages) RICHTEK

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RT6220

DS6220-11 July 2020

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

when input voltage drops below the UVLO-falling threshold.

The IC resumes switching when input voltage exceeds

the UVLO-rising threshold.

Over-Temperature Protection

The RT6220 features an Over-Temperature Protection

(OTP) circuitry to prevent overheating due to excessive

power dissipation. The OTP shuts down switching

operation when the junction temperature exceeds 150

°C.

Once the junction temperature cools down by

approximately 25

°C the IC resumes normal operation with

a complete soft-start. For continuous operation, provide

adequate cooling so that the junction temperature does

not exceed 150

°C. Note that the VCC regulator remains

on as the OTP is triggered.

Enable and Disable

The enable input (EN) has a logic-low level of 1.15V. When

VEN is below this level, the IC enters shutdown mode and

supply current drops to less than 5

μA (typical). Besides,

the switch-over switch is turned off and VCC LDO is also

powered off. When VEN exceeds its logic-high level (1.35V

typical), the IC is fully operational.

Soft-Start

The RT6220 provides an internal soft-start function to

prevent large inrush current and output voltage overshoot

when the converter starts up. The soft-start (SS)

automatically begins once the chip is enabled. During soft-

start, it clamps the ramp of internal reference voltage which

is compared with FB signal. And it will correct the output

voltage more accurately after soft-start. The typical soft-

start duration is 1.5ms.

Power Off

When VEN is pulled to GND or lower than the logic-low

level of 1.15V, there is an internal discharging resistor to

discharge the residual charge inside the output capacitors.

Besides, the value of discharging resistor is about twenty

ohms.

Power Good Output (PGOOD)

The power good output is an open-drain output that requires

a pull-up resistor. When the output voltage is 20% (typical)

below its set voltage, PGOOD will be pulled low. It is held

low until the output voltage returns to 90% of its set voltage

once more. During soft-start, PGOOD is actively held low

and only allowed to be pulled high after soft-start is over

and the output reaches 90% of its set voltage and the

PGOOD low to high delay(500

μs typical) has passed.

There is a 2

μs PGOOD high to low delay built into PGOOD

circuitry to prevent false triggering.

In addition, the PGOOD open drain driver is supplied by

VCC power source or VBYP pin voltage source in switch-

over mode. When converter is powered off by EN low signal,

the pull-low strength of PGOODopen drain driver decreases

after VCC voltage is lower than VCC_POR threshold (typ.

= 3.8V). As a result, the PGOOD pin is floated and pulled

up by external voltage source. In consideration of PGOOD

status after EN power off, it is recommended that

connecting PGOOD pin with a 100k

Ω resistor to VCC

(5V). DO NOT pull high to external voltage which is higher

than VCC (5V).

External Bootstrap Capacitor (CBOOT)

Connect a 0.1

μF low ESR ceramic capacitor between the

BOOT and SW pins. This bootstrap capacitor provides

the gate driver supply voltage for the high-side N-MOSFET

switch.

The internal power MOSFET switch gate driver is

optimized to turn the switch on fast enough for low power

loss and good efficiency, and slow enough to reduce EMI.

Switch turn-on is when most EMI occurs since VSW rises

rapidly. During switch turn-off, SW is discharged relatively

slowly by the inductor current during the dead-time

between high-side and low-side switch on-times. In some

cases it is desirable to reduce EMI further, at the expense

of some additional power dissipation. The switch turn-on

can be slowed by placing a small (<10

Ω) resistance

between BOOT and the external bootstrap capacitor. This

will slow the high-side switch turn-on and VSW's rise.

Setting the Output Voltage

The output voltage of the RT6220 is adjustable and with

valley control. There is an easy way to determine the output

voltage only by two resistors, R1 and R2. As the feedback

circuit shown in Figure 5. the relation of VOUT and VREF

can be derived as VOUT = (1+R1/R2) x VREF readily.

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