RT6220 datasheet(17/20 Pages) RICHTEK

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RT6220

DS6220-11 July 2020

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

of ceramic output capacitor (sag and soar are directly

proportional to capacitance) or adding extra bulk

capacitance can easily eliminate any excessive voltage

transients.

In any application with large quick transients, it should

calculate soar and sag to make sure that over-voltage

protection and under-voltage protection will not be triggered.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

where TJ(MAX) is the maximum junction temperature, TAis

the ambient temperature, and

θJAis the junction to ambient

thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125

°C. The junction to

ambient thermal resistance,

θJA, is layout dependent. For

UQFN-16L 3x3 (FC) package, the thermal resistance,

θJA,

is 43

°C/W on a high thermal conductivity four-layer

evaluation board made by Richtek. The maximum power

dissipation at TA = 25

°C can be calculated by the following

formula :

PD(MAX) = (125

°C − 25°C) / (43°C/W) = 2.33W for

UQFN-16L 3x3 (FC) package

The maximum power dissipation depends on the operating

ambient temperature for fixed TJ(MAX) and thermal

resistance,

θJA. The derating curve in Figure 6 allows the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

Figure 6. Derating Curve of Maximum Power Dissipation

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

100

125

Ambient Temperature (°C)

Four-Layer PCB

Layout Considerations

Layout is very important in high frequency switching

converter design. The PCB can radiate excessive noise

and contribute to converter instability with improper layout.

Certain points must be considered before starting a layout

using the RT6220.



Make traces of the high current paths as short and wide

as possible.



Put the input capacitor as close as possible to the device

pins (VIN and PGND).



The SW node encounters high frequency voltage swings

so it should be kept in a small area. Keep sensitive

components away from the SW node to prevent noise

coupling.



The PGND pin should be connected to a strong ground

plane for heat sinking and noise protection.



Avoid using vias in the power path connections that have

switched currents (from CIN to PGND and CIN to VIN)

and the switching node (SW).



The ground of VCC is recommended to connect to GND

layer through via, and the decoupling capacitor (CVCC)

should be placed near VCC pin. No via connection is

recommended.

An example of PCB layout guide is shown in Figure 7 for

reference.

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