BLN0 datasheet(13/18 Pages) AOSMD

13 / 18 page

AOZ5311NQI

Rev. 1.

2 April 2021

www.aosmd.com

Page 13 of 18

high-to-low and low-to-high transitions as well as Tri-

State window.

There is a Hold-off Delay between the corresponding

PWM Tri-State signal and the MOSFET gate drivers to

prevent spurious triggering of Tri-State mode which may

be caused by noise or PWM signal glitches. The Hold-off

Delay is typically 25ns.

Table 2. PWM Input and Tri-State Thresholds

Note: See Figure 2 for propagation delays and tri-state window.

Diode Mode Emulation of Low Side MOSFET

(SMOD#)

AOZ5311NQI can be operated in the diode emulation or

pulse skipping mode using SMOD# (Pin 2). This enables

the converter to operate in asynchronous mode during

start up, light load or under pre-bias conditions.

When SMOD# is high, the module will operate in

Continuous Conduction Mode (CCM). The Driver logic

will use the PWM signal and generate both the High-Side

and Low-Side complementary gate drive outputs with

minimal anti-overlap delays to avoid cross conduction.

When SMOD# is low, the module can operate in

Discontinuous Conduction Mode (DCM). The High-Side

MOSFET gate drive output is not affected but Low-Side

MOSFET will enter diode emulation mode. See Table 2

for all truth table for DISB#, SMOD# and PWM inputs.

Gate Drives

AOZ5311NQI has an internal high current high speed

driver that generates the floating gate driver for the High-

Side MOSFET and a complementary driver for the Low-

Side MOSFET. An internal shoot through protection

scheme is implemented to ensure that both MOSFETs

cannot be turned on at the same time. The operation of

PWM signal transition is illustrated as below.

1. PWM from logic Low to logic High

When the falling edge of Low-Side Gate Driver output GL

goes below 1V, the blanking period is activated. After a

pre-determined value (tPDHU), the complementary High-

Side Gate Driver output GH is turned on.

2. PWM from logic High to logic Low

When the falling edge of switching node VSWH goes

below 1V, the blanking period is activated. After a pre-

determined value (tPDHL), the complementary Low-Side

Gate Driver output GL is turned on

This mechanism prevents cross conduction across the

input bus line VIN and PGND. The anti-overlap circuit

monitors the switching node VSWH to ensure a smooth

transition between the two MOSFETs under any load

transient conditions.

Thermal Warning (THWN)

The driver IC temperature is internally monitored and an

thermal warning flag at THWN (Pin 30) is asserted if it

exceeds 150°C. This warning flag is reset when the

temperature drop back to 120°C. THWN is an open drain

output that is pulled to AGND to indicate an over-

temperature condition. It should be connected to VCC

through a resistor for monitoring purpose. The device

will not power down during the over temperature

condition.

PCB Layout Guidelines

AOZ5311NQI is a high current module rated for

operation up to 2MHz. This requires fast switching

speed to keep the switching losses and device

temperatures within limits. An integrated gate driver

within the package eliminates driver-to-MOSFET gate

pad parasitic of the package or on PCB.

To achieve high switching speeds, high levels of slew

rate (dv/dt and di/dt) will be present throughout the

power train which requires careful attention to PCB

layout to minimize voltage spikes and other transients.

As with any synchronous buck converter layout, the

critical requirement is to minimize the path of the primary

switching current loop formed by the High-Side MOSFET,

Low-Side MOSFET, and the input bypass capacitor CIN.

The PCB design is greatly simplified by the optimization

of the AOZ5311NQI pin out. The power inputs of VIN

and PGND are located adjacent to each other and the

input bypass capacitors CIN should be placed as close

as possible to these pins. The area of the secondary

switching loop is formed by Low-Side MOSFET, output

inductor L1, and output capacitor COUT is the next

critical requirement. This requires second layer or “Inner

1” to be the PGND plane. VIAs should then be placed

near PGND pads.

While AOZ5311NQI is a highly efficient module, it is still

dissipating significant amount of heat under high power

conditions. Special attention is required for thermal

design. MOSFETs in the package are directly attached to

individual exposed pads (VIN and PGND) to simplify

thermal management. Both VIN and VSWH pads should

be attached to large areas of PCB copper. Thermal relief

pads should be placed to ensure proper heat dissipation

to the board. An inner power plane layer dedicated to

VIN, typically the high voltage system input, is desirable

and VIAs should be provided near the device to connect

the VIN pads to the power plane. Significant amount of

Thresholds



VPWMH

VPWML

VTRIH

VTRIL

AOZ5311NQI

2.7 V

0.72 V

1.35 V

2.1 V

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