MAQ430 – 12-BIT, AUTOMOTIVE ANGLE SENSOR WITH ABZ & UVW OUTPUTS

MAQ430 Rev. 1.2

www.MonolithicPower.com

24

8/8/2022

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Table 17: Register 4 and Register 5

B7

B6

B5

B4

B3

B2

B1

B0

R4

1

1

0

0

0

0

0

0

R5

0

0

0

1

1

1

0

1

Figure 22: Timing of the ABZ Output

Signal Z (zero or index) raises only once per

turn at the zero-angle position.

The position and length of the Z pulse is

programmable via bit ILIP(3:0) in register 0x4

(see Figure 23).

Figure 23: ILIP Parameter Effect on Index Shape

By default, the ILIP parameter is 0000. The

index rising edge is aligned with the channel B

falling edge and the index length is half the A or

B pulse length.

ABZ Hysteresis

A hysteresis larger than the output noise is

introduced on the ABZ output to prevent any

spurious transitions (see Figure 24).

Figure 24: Hysteresis of the Incremental

OutputABZ Jitter

The ABZ state is updated at a frequency of

16MHz, enabling accurate operation up to a

very high rpm (above 105 rpm).

The jitter characterizes how far a particular ABZ

edge can occur at an angular position different

from the ideal position (see Figure 25).

Figure 25: ABZ Jitter

The

measurable

jitter

is

composed

of

a

systematic jitter (always the same deviation at a

given angle) and a random jitter.

The random jitter reflects the sensor noise, so

the edge distribution is the same as the SPI

output noise. Like the sensor resolution, it is

defined as the 3σ width of this distribution.

The random jitter is a function of the rotation

speed. At lower speeds, the random jitter is

smaller than the sensor noise (see the Typical

Characteristic curves on page 7).

This is a consequence of the fact that the

probability of measuring an edge at a certain

distance from the ideal position depends on the

number of ABZ updates at this position.

The minimum field for ABZ reading is 30mT.

Block Commutation – UVW

The UVW output emulates the three Hall

switches

usually

used

for

the

block

commutation of a three-phase electric motor.

The three logic signals have a duty cycle of

50% and are shifted by 60° relative to each

other (see Figure 26 on page 25).