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ES9033Q Datasheet(PDF) 78 Page - ESS Technology,Inc |
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ES9033Q Datasheet(HTML) 78 Page - ESS Technology,Inc |
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78 / 103 page  a 0.3.1 ES9033 Datasheet Information ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 78 Register 77-76: DRE GAIN CH2 Bits [15:0] Default 16’h1A34 Bits Mnemonic Description [15:0] DRE_GAIN2 Sets the DRE gain for CH2. Shift right 1 bit corresponds to - 6dB. • 16’h07FF (0dB): Minimum • 16’h1A34 (16.33dB): Default • 16’h7FFF (30dB): Maximum Register 79-78: DRE ON THRESHOLD Bits [15:0] Default 16’h0CF1 Bits Mnemonic Description [15:0] DRE_ON_THRESH DRE on threshold. Shift right 1 bit corresponds to -6dB. • 16’h0CF1 (-48dB): Default • 16’hFFFF (-24dB): Maximum Register 81-80: DRE OFF THRESHOLD Bits [15:0] Default 16’h8184 Bits Mnemonic Description [15:0] DRE_OFF_THRESH DRE off threshold. Shift right 1 bit corresponds to -6dB. • 16’h8184 (-28dB): Default • 16’hFFFF (-24dB): Maximum |
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