ES9080 datasheet(87/146 Pages) ESS

87 / 146 page

CONFIDENTIAL ADVANCE INFORMATION 0.4.3

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

ES9080 Product Datasheet

Bits

[7:5]

[4]

[3]

[2]

[1]

[0]

Default

3'd0

1'b0

Bits

Mnemonic

Description

[7:5]

RESERVED

[4]

SYNC_DAC_CLK_DIV

Controls clock divider reset on negative edge of WS.

•

1’b1: Clock divider will be reset at every negative edge

of WS

•

1’b0: Disable the FIR_RESYNC reset

Note: If reset the SYNC_DAC_CLK_DIV (ie 1’b1), toggle this

bit before setting any other RESYNC bits [3:0]

[3]

DOP_CLK_RESYNC

Controls Dop clock divider reset on negative edge of WS.

•

1’b1: Clock divider will be reset at every negative edge

of WS

•

1’b0: Disable the FIR_RESYNC reset

[2]

VOL_THD_RESYNC

Controls Volume-THD block reset on negative edge of WS.

•

1’b1: DoP clock generator will be reset at every

negative edge of WS

•

1’b0: Disable the DOP_CLK_RESYNC reset

[1]

FIR_RESYNC

Controls FIR filters reset on negative edge of WS.

•

1’b1: FIR filters will be reset at every negative edge of

•

1’b0: Disable the FIR_RESYNC reset

[0]

FS_RESYNC

Controls FS clock generator reset on negative edge of WS.

•

1’b1: FS clock generator will be reset at every

negative edge of WS

•

1’b0: Disable the FS_RESYNC reset

Bits

[7:0]

Default

8'd0

Bits

Mnemonic

Description

[7:0]

VOLUME1

DAC ch1 volume. -0dB to -127.5dB 0.5dB steps.

•

8'd0: 0dB

•

8'd255: -127.5 dB

ES9080 Datasheet(PDF) 87 Page - ESS Technology,Inc

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