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WM8706SEDS/R Datasheet(PDF) 11 Page - Wolfson Microelectronics plc

Part # WM8706SEDS/R
Description  24-bit, 192kHz Stereo DAC with Volume Control
PDF  26 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8706SEDS/R Datasheet(HTML) 11 Page - Wolfson Microelectronics plc

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WM8706
Production Data
w
PD Rev 4.1 July 2005
11
In left justified, right justified and I
2S modes, the minimum number of BCKINs per LRCIN period
is 2 times the selected word length. LRCIN must be high for a minimum of word length BCKINs
and low for a minimum of word length BCKINs. Any mark to space ratio on LRCIN is
acceptable provided the above requirements are met. The WM8706 will automatically detect
when data with a LRCIN period of exactly 32 is sent, and select 16 bit mode - overriding any
previously programmed word length. Word length will revert to the previously programmed
value when a LRCIN period other than 32 is detected. (see Figure 4, Figure 5 and Figure 6).
In DSP early or DSP late mode, the data is time multiplexed onto DIN. LRCIN is used as a
frame sync signal to identify the MSB of the first word. The minimum number of BCKINs per
LRCIN period is 2 times the selected word length. Any mark to space ratio is acceptable on
LRCIN provided the rising edge is correctly positioned (see Figure 7 and Figure 8).
LEFT JUSTIFIED MODE
In left justified mode, the MSB is sampled on the first rising edge of BCKIN following a LRCIN
transition. LRCIN is high during the left samples and low during the right samples.
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
Figure 4 Left Justified Mode Timing Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN
transition. LRCIN is high during the left samples and low during the right samples.
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
Figure 5 Right Justified Mode Timing Diagram



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