WM8706

Production Data

w

PD Rev 4.1 July 2005

12

I

In I

transition. LRCIN is low during the left samples and high during the right samples.

LEFT CHANNEL

RIGHT CHANNEL

LRCIN

BCKIN

DIN

1/fs

n

3

2

1

n-2 n-1

LSB

MSB

n

3

2

1

n-2 n-1

LSB

MSB

1 BCKIN

1 BCKIN

Figure 6 I

DSP EARLY MODE

In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one which

detects a low to high transition on LRCIN. No BCKIN edges are allowed between the data

words. The word order is DIN left, DIN right.

LRCIN

BCKIN

DIN

Input Word Length (IWO)

1/fs

LEFT CHANNEL

n

2

1

n-1

LSB

MSB

n

2

1

n-1

RIGHT CHANNEL

NO VALID DATA

1 BCKIN

1 BCKIN

Figure 7 DSP Early Mode Timing Diagram

DSP LATE MODE

In DSP late mode, the first bit is sampled on the BCKIN rising edge which detects a low to high

transition on LRCIN. No BCKIN edges are allowed between the data words. The word order is

DIN left, DIN right.

LRCIN

BCKIN

DIN

Input Word Length (IWO)

1/fs

LEFT CHANNEL

n

2

1

n-1

LSB

MSB

n

2

1

n-1

RIGHT CHANNEL

NO VALID DATA

1

Figure 8 DSP Late Mode Timing Diagram