WM8706

Production Data

w

PD Rev 4.1 July 2005

19

POWERDOWN MODE

mode. All trace of the previous input samples is removed, and all register settings are cleared.

When PWDN is cleared again the first 16 input samples will be ignored as the FIR will repeat

it's power-on initialisation sequence.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

010

DAC Control

2

PWDN

0

Power Down Mode Select:

0 : Normal Mode

1: Power Down Mode

Table 13 Powerdown Control

DIGITAL AUDIO INTERFACE CONTROL REGISTERS

The WM8706 has a fully featured digital audio interface that is a superset of that contained in

the WM8716. Interface format is selected via the IW[2:0] register bits in register M2 and the I

register bit in M3.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

010

DAC Control

5:3

IW[2:0]

000

Interface format Select

Table 14 Interface Format Controls

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

011

Interface Control

0

I

0

Interface format Select

Table 15 Interface Format Control

IW2

I

IW1

IW0

AUDIO INTERFACE DESCRIPTION **

0

0

0

0

16 bit right justified mode

0

0

0

1

20 bit right justified mode

0

0

1

0

24 bit right justified mode

0

0

1

1

24 bit left justified mode

0

1

0

0

16 bit I

0

1

0

1

24 bit I

0

1

1

0

20 bit I

0

1

1

1

20 bit left justified (MSB first) mode

1

0

0

0

16 bit DSP mode

1

0

0

1

20 bit DSP mode

1

0

1

0

24 bit DSP mode

1

0

1

1

32 bit DSP mode

1

1

0

0

16 bit left justified mode

Table 16 Audio Data Input Format

Note:

** In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If

the DAC is programmed to receive 16 or 20 bit data, the WM8706 pads the unused LSBs with

zeros. If the DAC is programmed into 32 bit mode, the 4 LSBs are ignored.

SELECTION OF LRCIN POLARITY

In left justified, right justified or I

this bit is set high, the expected polarity of LRCIN will be the opposite of that shown in Figure 4,

Figure 5 and Figure 6. Note that if this feature is used as a means of swapping the left and

right channels, a 1 sample phase difference will be introduced.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

011

Interface Control

1

LRP

0

LRCIN Polarity (normal)

0 : normal LRCIN polarity

1: inverted LRCIN polarity

Table 17 LRCIN Polarity Control