AD8370 datasheet(14/28 Pages) AD

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AD8370

Rev. A | Page 14 of 28

OUTPUT AMPLIFIER

Table 4. Serial Programming Timing Parameters

Parameter

Min

Unit

The output impedance is approximately 100 Ω differential and,

like the input preamplifier, this impedance is formed using

active circuit elements. See Figure 40 for a simplified schematic

of the output interface.

Clock Pulse Width (TPW)

Clock Period (TCK)

Setup Time Data vs. Clock (TDS)

Setup Time Latch vs. Clock (TES)

VCC/2

740

OPHI/OPLO

Hold Time Latch vs. Clock (TEH)

μA

CLCK/DATA/LTCH/PWUP

Figure 42. Simplified Circuit for Digital Inputs

Figure 40. OPHI/OPLO Simplified Circuit

The gain of the output amplifier, and thus the AD8370 as a

whole, is load dependent. The following equation can be used to

predict the gain deviation of the AD8370 from that at 100 Ω as

the load is varied.

VCC/2

VOCM

LOAD

ion

GainDeviat

For example, if RLOAD is 1 kΩ, the gain is a factor of 1.80 (5.12 dB)

above that at 100 Ω, all other things being equal. If RLOAD is 50

Ω, the gain is a factor of 0.669 (3.49 dB) below that at 100 Ω.

Figure 43. Simplified Circuit for VOCM Output

DIGITAL INTERFACE AND TIMING

The digital control port uses a standard TTL interface. The 8-bit

control word is read in a serial fashion when the LTCH pin is

held low. The levels presented to the DATA pin are read on each

rising edge of the CLCK signal. Figure 41 illustrates the timing

diagram for the control interface. Minimum values for timing

parameters are presented in Table 4. Figure 42 is a simplified

schematic of the digital input pins.

DATA

(PIN 14)

CLCK

(PIN 13)

LTCH

(PIN 12)

TDS

TES

TEH

MSB

MSB-1 MSB-2 MSB-3

LSB

LSB+1

LSB+2

LSB+3

TCK

TPW

Figure 41. Digital Timing Diagram

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