AD1994 datasheet(16/24 Pages) AD

16 / 24 page

AD1994

Rev. 0 | Page 16 of 24

Power-Up Sequencing

When the load impedance is substantially less than 4 Ω, the

system would be current limited if configured for normal stereo

operation, and the amplifier would enter the overcurrent error

state when a nominal input signal is applied. Under these

conditions, the amount of real power delivered to the load

increases in mono mode. The minimum recommended

impedance in mono mode is 2 Ω (as compared to 4 Ω for stereo

operation), so the effective power delivered to a single channel

can be as much as twice the maximum achievable in stereo mode.

Careful power-up is necessary when using the AD1994 to

ensure correct operation and to avoid possible latch-up issues.

The AD1994 should be powered up with RESET

MUTE

and

held low until all the power supplies have stabilized. Once the

supplies have stabilized, bring the AD1994 out of RESET by

bringing RESET high.

MUTE

Begin the soft unmute sequence by bringing

high at

least 1 sec after the RESET rising edge. The amplifier produces

audio using a shorter start-up sequence (as shown in

For reactive loads, the impedance can only be below the

recommended threshold over a small portion of the amplifier’s

bandwidth. In these cases, the amplifier can enter overcurrent

shutdown in response to even small input signals in those

frequency bands. When designing a system, use the minimum

load impedance over the entire range of amplified frequencies

when calculating current output rather than the average or

nominal load impedance ratings often cited by loudspeaker

driver manufacturers.

Table 7),

but the amplifier can produce an audible pop or click noise as

the output starts switching. This is because the ac coupling

capacitors at the analog input have a long time constant. If

MUTE is deasserted substantially less than 1 sec after deasserting

RESET, then these capacitors may not have charged to a steady

state. They need ample time to settle at a bias voltage of VREF,

the reference voltage for the single-ended inputs, or the

amplifier starts with a slight dc offset.

MODULATOR MODE

MONO MODE

The AD1994 is capable of operating as a modulator for controlling

external power devices. When MOD_EN (Pin 49) is logic level

high at the rising edge of

The power supply voltage and the limited current that the

output transistors can source combine to dictate that maximum

total output power of the AD1994. For higher impedance loads,

the system is voltage limited, and for lower impedance loads,

the system is current limited. In normal stereo operation, each

output is driven by four MOSFET devices arranged in a full

H-bridge configuration, also known as bridge-tied load (BTL).

This provides the maximum differential output voltage swing,

equal to twice the voltage of the power supply. However,

operating in mono mode doubles the maximum achievable

output current.

RESET, both the left and right internal

power stages are disabled. The error output flags (

When MONO_EN (Pin 64) is logic level high at the rising edge

of RESET, the right channel modulator is disabled, and the left

channel modulator is used to drive both the left and right

output stages in parallel. When using mono mode, connect

OUTL+ directly to OUTR+, connect OUTL− directly to

OUTR−, and use the combined differential pair to a drive a

single load. Connect the feedback pair to the positive and

negative feedback input of the left modulator. The right

channel feedback pins are unused in mono mode. The RDS-ON

of the power FETs drops to half of its value in stereo operation

because the devices are in parallel, and the AD1994 delivers its

full current capability to a single channel.

Note that the practical effect of mono mode depends greatly on

the load impedance. If the load is 4 Ω or greater, the efficiency

of the amplifier increases due to the reduced effective resistance

of power FETs, and the amplifier dissipates less heat. However,

the amount of real power delivered to the load does not increase

because the system is voltage limited (that is, the output

waveform voltage clips before current limiting occurs).

ERR2 ERR1

and ERR0) and the nonoverlap delay inputs (DCNTL2, DCNTL1,

and DCNTL0) no longer have meaning because they apply only

to the internal power stages. The logic level outputs from the

two modulators appear on Pin 19 (MODL) and Pin 20 (MODR).

GAIN STRUCTURE

Analog Input Levels

The AD1994 has single-ended inputs for the left and right

channels. The analog input section uses an internal amplifier to

bias the input signal to the reference level, VREF, which is nominally

equal to AV /2. A dc-blocking capacitor, as shown in Figure 44

prevents this bias voltage from affecting the signal source. In

combination with the nominal 20 kΩ input impedance, the value

of this capacitor should be large enough to produce a flat

frequency response at the lowest input frequency of interest.

Note that the amplifier is capable of dc-coupled operation if the

circuit includes some means to account for this bias voltage.

AINL/

AINR

Figure 44. AC-Coupled Input Signal

AD1994 Datasheet(PDF) 16 Page - Analog Devices

AD1994 Datasheet(HTML) 16 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL