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10.4 Power Supply Recommendations

These devices are designed to operate from an input supply with a voltage range between 1.4 V (VPOR) to 65 V

(max operation). Good analog design practice recommends placing a minimum 0.1 µF ceramic capacitor as near

as possible to the VDD pin.

10.4.1 Power Dissipation and Device Operation

The permissible power dissipation for any package is a measure of the capability of the device to pass heat from

the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus, the power

dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces

between the die junction and ambient air.

The maximum continuous allowable power dissipation for the device in a given package can be calculated using

Equation 12:

PD-MAX = ((TJ-MAX – TA) / RθJA)

(12)

The actual power being dissipated in the device can be represented by Equation 13:

PD = VDD × IDD + pRESET

(13)

pRESET is calculated by Equation 14 or Equation 15

pRESET (PUSHPULL) = VDD - VRESET x IRESET

(14)

pRESET (OPEN-DRAIN) = VRESET x IRESET

(15)

Equation 12 and Equation 13 establish the relationship between the maximum power dissipation allowed due to

thermal consideration, the voltage drop across the device, and the continuous current capability of the device.

These two equations should be used to determine the optimum operating conditions for the device in the

application.

In applications where lower power dissipation (PD) and/or excellent package thermal resistance (RθJA) is

present, the maximum ambient temperature (TA-MAX) may be increased.

In applications where high power dissipation and/or poor package thermal resistance is present, the maximum

ambient temperature (TA-MAX) may have to be de-rated. TA-MAX is dependent on the maximum operating junction

temperature (TJ-MAX-OP = 125°C), the maximum allowable power dissipation in the device package in the

application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA),

as given by Equation 16:

TA-MAX = (TJ-MAX-OP – (RθJA × PD-MAX))

(16)

10.5 Layout

10.5.1 Layout Guidelines

• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a

greater than 0.1 µF ceramic capacitor as near as possible to the VDD pin.

• To further improve the noise immunity on the SENSEx pins, placing a 10 nF to 100 nF capacitor between the

SENSEx pins and GND can reduce the sensitivity to transient voltages on the monitored signal.

• If a capacitor is used on CTS1, CTS2, CTR1, or CTR2, place these components as close as possible to the

respective pins. If the capacitor adjustable pins are left unconnected, make sure to minimize the amount of

parasitic capacitance on the pins to less than 5 pF.

• For open-drain variants, place the pull-up resistors on RESET1 and RESET2 pins as close to the pins as

possible.

• When laying out metal traces, separate high voltage traces from low voltage traces as much as possible. If

high and low voltage traces need to run close by, spacing between traces should be greater than 20 mils

(0.5 mm).

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TPS37-Q1

SNVSBD9E – AUGUST 2020 – REVISED AUGUST 2023

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