ATMEGA644 datasheet(20/374 Pages) ATMEL

20 / 374 page

2593L–AVR–02/07

ATmega644

The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and the

4096 bytes of internal data SRAM in the ATmega644 are all accessible through all these

addressing modes. The Register File is described in ”General Purpose Register File” on page

12.

Figure 6-2.

Data Memory Map

6.2.1

Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk

CPU cycles as described in Figure 6-3.

Figure 6-3.

On-chip Data SRAM Access Cycles

6.3

EEPROM Data Memory

The ATmega644 contains 2K bytes of data EEPROM memory. It is organized as a separate

data space, in which single bytes can be read and written. The EEPROM has an endurance of at

least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described

in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and

the EEPROM Control Register.

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see

page 298, page 302, and page 286 respectively.

32 Registers

64 I/O Registers

Internal SRAM

(4096 x 8)

$0000 - $001F

$0020 - $005F

$10FF

$0060 - $00FF

$0100

Data Memory

160 Ext I/O Reg.

clk

Data

Address

Address valid

Compute Address

CPU

Memory Access Instruction

Next Instruction

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