ATMEGA644 datasheet(63/374 Pages) ATMEL

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2593L–AVR–02/07

ATmega644

11. External Interrupts

The External Interrupts are triggered by the INT2:0 pin or any of the PCINT31:0 pins. Observe

that, if enabled, the interrupts will trigger even if the INT2:0 or PCINT31:0 pins are configured as

outputs. This feature provides a way of generating a software interrupt.

The Pin change interrupt PCI3 will trigger if any enabled PCINT31:24 pin toggle, Pin change

interrupt PCI2 will trigger if any enabled PCINT23:16 pin toggles, Pin change interrupt PCI1 if

any enabled PCINT15:8 toggles and Pin change interrupts PCI0 will trigger if any enabled

PCINT7:0 pin toggles. PCMSK3, PCMSK2, PCMSK1 and PCMSK0 Registers control which pins

contribute to the pin change interrupts. Pin change interrupts on PCINT31:0 are detected asyn-

chronously. This implies that these interrupts can be used for waking the part also from sleep

modes other than Idle mode.

The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up

as indicated in the specification for the External Interrupt Control Registers – EICRA (INT2:0).

When the external interrupt is enabled and is configured as level triggered, the interrupt will trig-

ger as long as the pin is held low. Low level interrupts and the edge interrupt on INT2:0 are

detected asynchronously. This implies that these interrupts can be used for waking the part also

from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle

mode.

Note that if a level triggered interrupt is used for wake-up from Power-down, the required level

must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If

the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-

rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described

in ”System Clock and Clock Options” on page 28.

11.0.1

EICRA – External Interrupt Control Register A

The External Interrupt Control Register A contains control bits for interrupt sense control.

• Bits 7:6 – Reserved

These bits are reserved in the ATmega644, and will always read as zero.

• Bits 5:0 – ISC21, ISC20 – ISC00, ISC00: External Interrupt 2 - 0 Sense Control Bits

The External Interrupts 2 - 0 are activated by the external pins INT2:0 if the SREG I-flag and the

corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that

activate the interrupts are defined in Table 11-1. Edges on INT2:INT0 are registered asynchro-

nously. Pulses on INT2:0 pins wider than the minimum pulse width given in Table 11-2 will

generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level

interrupt is selected, the low level must be held until the completion of the currently executing

instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an inter-

rupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur.

Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the

EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be

cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the

interrupt is re-enabled.

Bit

76543210

(0x69)

–

ISC21

ISC20

ISC11

ISC10

ISC01

ISC00

EICRA

Read/Write

R/W

Initial Value

00000000

ATMEGA644 Datasheet(PDF) 63 Page - ATMEL Corporation

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