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AAT3141 Datasheet(PDF) 12 Page - Advanced Analog Technology, Inc. |
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AAT3141 Datasheet(HTML) 12 Page - Advanced Analog Technology, Inc. |
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12 / 16 page ![]() AAT3141 High Efficiency 1X/1.5X/2X Charge Pump for White LED Applications 12 3141.2007.03.1.3 AS 2Cwire Serial Interface The current source output magnitude is controlled by the AS 2Cwire serial digital input. AS2Cwire adds addressing capability for multiple data registers over the Simple Serial Control™ (S 2Cwire™), which is only capable of controlling a single regis- ter. The AAT3141 has two registers. One contains the current level setting for outputs D1 to D3, and the other contains the current level setting for out- put D4. Three addresses are used to control the two regis- ters. Address 0 addresses both registers simulta- neously to allow the loading of both registers with the same data using a single write protocol. Address 1 addresses Register 1 for D1 to D3 cur- rent level settings. Address 2 addresses Register 2 for D4 current level settings. As with S 2Cwire, AS2Cwire relies on the number of rising edges of the EN/SET pin to address and load the registers. AS 2Cwire latches data or address after the EN/SET pin has been held high for time T LAT. Address or data is differentiated by the num- ber of EN/SET rising edges. Since the data regis- ters are 5 bits each, the differentiating number of pulses is 2 5 or 32, so that Address 0 is signified by 33 rising edges, Address 1 by 34 rising edges and Address 2 by 35 rising edges. Data is set to any number of rising edges between 1 and including 32. A typical write protocol is a burst of EN/SET ris- ing edges, signifying a particular address, followed by a pause with EN/SET held high for the T LAT time- out period, a burst of rising edges signifying data, and a T LAT timeout for the data registers. Once an address is set, then multiple writes to the corre- sponding data register are allowed. Address 0 is the default address on the first rising edge after the AAT3141 has been disabled. If data is presented on the first rising edge with no prior address, both data registers are simultaneously loaded. When EN/SET is held low for an amount of time greater than T OFF, the AAT3141 enters into shutdown mode and draws less than 1µA from V IN. Data and address registers are reset to 0 during shutdown. Table 2: AS 2Cwire Serial Interface Addressing. AS 2Cwire Serial Interface Timing Address EN/SET Rising Edges Data Register 0 33 1 & 2: D1-D4 1 34 1: D1-D3 2 35 2: D4 Address Data 1 EN/SET 2 33 34 Address Data Reg 1 Data Reg 2 1 2 . . . n <= 32 0 1 0 0 n THI TLO TLAT TLAT |
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