AFE78201 datasheet(21/95 Pages) TI

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7 Detailed Description

7.1 Overview

The AFEx8201 feature a 16-bit (AFE88201) or 14

‑bit (AFE78201) string DAC with voltage output buffer. Both

devices have a buffered voltage output and are designed for use in three

‑wire or four-wire sensor transmitters

or analog output modules. The DAC has calibration registers for setting gain and offset values for adjusting the

DAC outputs. The DAC also has different output slewing modes that allow for a programmable linear slew and a

sinusoidal shaped output slew.

The AFEx8201 also feature a 12

‑bit SAR ADC that can be multiplexed to measure different inputs, including

external nodes and internal nodes for diagnostic measurements on the device. The ADC is capable of making

direct-mode measurements with on-demand conversions or auto-mode measurements through continuous

conversions using a channel sequencer with a multiplexer. The devices have optional alarm configurations with

fault detection and alarm actions.

Device communication and programming are done through an SPI or through the UART break mode (UBM).

With the SPI, a cyclic redundancy check (CRC) is implemented by default, which can be disabled. Additionally,

communications can be monitored with a watchdog timer (WDT) that alerts the user if the device becomes

unresponsive to periodic communication.

The AFEx8201 feature a 1.25-V, onboard precision voltage reference, and an integrated precision oscillator.

Throughout this data sheet, register and bit names are combined with a period to use the following format:

<register_name>.<bit_name>. For example, the CLR bit in the DAC_CFG register is labeled DAC_CFG.CLR.

7.2 Functional Block Diagram

MUX

12-Bit ADC

MUX

Internal

Diagnostics

Temperature

Sensor

AIN0

POL_SEL/AIN1

16-/14-Bit

DAC

VOUT

Alarm

Diagnostics

Alarm

Responses

User

Calibration

Slew-Rate

Control

DAC Data

Watchdog

Timer

CRC Frame

Error Check

ALARM

Control Logic

PVDD

VDD

GND

Internal

Reference

VREFIO

REF_EN

IOVDD

Internal

Oscillator

IRQ (UARTOUT or SDO)

Output Buffer

Range Setting

2.7-V

Comparator

1.8-V

LDO

Power-

Reset

OTP

IOVDD

PVDD

VDD

VREF

PVDD

Bias

Generator

0.6 V

ZTAT

REF_GND

GPIO0/CLK_OUT

SCLK

SCLR

GPIO1

RESET

GPIO5/SDI

GPIO4/SDO

GPIO3/UARTIN

GPIO2/UARTOUT

GPIO6/CS

PVDD

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AFE78201, AFE88201

SLASF44 – MAY 2023

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