1997 May 14

15

Philips Components

Preliminary specification

Desktop video & FM radio module

system CCIR I

FM1246

Start - Adb - Ack - Db1 - Ack - Db2 - Ack - Cb - Ack - Pb - Ack - Stop.

Start - Adb - Ack - Cb - Ack - Pb - Ack - Db1 - Ack - Db2 - Ack - Stop.

Start - Adb - Ack - Db1 - Ack - Db2 - Ack - Cb - Ack - Stop.

Start - Adb - Ack - Db1 - Ack - Db2 - Ack - Stop.

Where:

Start = start condition

Adb = address byte

Ack = acknowledge

Db1 = divider byte 1

Db2 = divider byte 2

Cb = control byte

Pb = ports byte

Stop = stop condition.

READ mode

The in-lock can be read by setting the R/W bit to 1.

Notes

data is detected by the PLL IC.

2. FL = In-lock flag; FL = 1: loop is phase-locked. The loop must be phase-locked during at least 8 periods of the internal

reference frequency (either 7.8125 kHz, 3.90625 kHz or 6.25 kHz) before the FL flag is internally set to 1.

3. I2, I1 and I0 = digital information for I/O ports P2, P1 and P0 respectively.

4. A2, A1 and A0 = built-in 5-level A/D converter on the internal I/O port P6 (see Table “Digital AFC status”).

5. A = Acknowledge.

Start - Adb - Ack - STB - Ack - STB - - Stop (no Ack from processor = End-of-data).

Start - Adb - Ack - STB - - Stop (no Ack from processor = End-of-data).

Where:

STB = Status byte.

BYTE

BITS

7

MSB

654321

0

LSB

Address byte

1

1

0

0

0

MA1

MA0

1

A

Status byte

A