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ES8328 Datasheet(PDF) 11 Page - Suzhou Everest Semiconductor Co. Ltd. |
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ES8328 Datasheet(HTML) 11 Page - Suzhou Everest Semiconductor Co. Ltd. |
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11 / 37 page  Everest Semiconductor ES8328 difference from the I2C protocol. Table 3 Write Data to Register in 2-wire Interface Mode Chip Address R/W Register Address Data to be written 001000 AD0 0 ACK RAM ACK DATA Table 4 Read Data from Register in 2-wire Interface Mode Chip Address R/W Register Address 001000 AD0 0 ACK RAM Chip Address R/W Data to be read 001000 AD0 1 ACK DATA 6 CONFIGURATION REGISTER DEFINITION SPI and 2-wire configuration interface share the same registers because there is only one interface active at any time. There are total of 53 user programmable 8-bit registers in this device. These registers control the operations of ADC and DAC. External master controller can access these registers by using the slave address specified in RAM (Register Address Map) register as shown in the Table 5. Table 5 Bit Content of Register Address Map B7 B6 B5 B4 B3 B2 B1 B0 Reg. 00 SCPReset LRCM DACMCLK SameFs SeqEn EnRef VMIDSEL Reg. 01 TSDEN PdnOC LPVcmMod LPVrefBuf PdnAna PdnIbiasgen VrefrLo PdnVrefbuf Reg. 02 adc_DigPDN dac_DigPDN adc_stm_rst dac_stm_rst ADCDLL_PDN DACDLL_PDN adcVref_PDN dacVref_PDN Reg. 03 PdnAINL PdnAINR PdnADCL PdnADCR PdnMICB PdnADCBiasgen flashLP int1LP Reg. 04 PdnDACL PdnDACR LOUT1 ROUT1 LOUT2 ROUT2 MONO OUT3 Reg. 05 LPDACL LPDACR LPLOUT1 OC[2] LPLOUT2 OC[3] LPMONO LPOUT3 Reg. 06 LPPGA LPLMIX LPRMIX LPMMIX LPMOUTINV LPOUT2INV LPADCvrp LPDACvrp Reg. 07 VSEL Reg. 08 MSC MCLKDIV2 BCLK_INV BCLKDIV Reg. 09 MicAmpL MicAmpR Reg. 10 LINSEL RINSEL Reg. 11 DS MONOMIX TRI OC[1:0] Reg. 12 DATSEL ADCLRP ADCWL ADCFORMAT Reg. 13 ADCFsMode ADCFsRatio Reg. 14 ADC_invL ADC_invR ADC_HPF_L ADC_HPF_R Reg. 15 ADCRampRate ADCSoftRamp ADCZeroCrs ADCLeR ADCMute Reg. 16 LADCVOL Reg. 17 RADCVOL Reg. 18 ALCSEL MAXGAIN MINGAIN Reg. 19 ALCLVL ALCHLD Revision 1.0 8/15/2009 11 |
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