ES8328 datasheet(13/37 Pages) EVEREST

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Everest Semiconductor

ES8328

1 – ALRCK and DLRCK disabled when all ADC and DAC disabled

DACMCLK

0 – when SameFs=1, ADCMCLK is the chip master clock source (default)

1 – when SameFs=1, DACMCLK is the chip master clock source

SameFs

0 – ADC Fs differs from DAC Fs (default)

1 – ADC Fs is the same as DAC Fs

SeqEn

0 – internal power up/down sequence disable (default)

1 – internal power up/down sequence enable

EnRef

0 – disable reference

1 – enable reference (default)

VMIDSEL

1:0

00 – Vmid disabled

01 – 50 k

Ω divider enabled

10 – 500 k

Ω divider enabled (default)

11 – 5 k

Ω divider enabled

6.1.2 Register 1 – Chip Control 2, Default 0001 1100

Bit Name

Bit

Description

TSDEN

0 – thermal shutdown disabled (default)

1 – thermal shutdown enabled

PdnOC

0 – over current shutdown disabled (default)

1 – over current shutdown enabled

LPVcmMod

0 – normal (default)

1 – low power

LPVrefBuf

0 – normal

1 – low power (default)

PdnAna

0 – normal

1 – entire analog power down (default)

PdnIbiasgen

0 – normal

1 – ibiasgen power down (default)

VrefLo

0 – normal (default)

1 – low power

PdnVrefbuf

0 – normal (default)

1 – power down

6.1.3 Register 2 – Chip Power Management, Default 1100 0011

Bit Name

Bit

Description

adc_DigPDN

0 – normal

1 – resets ADC DEM, filter and serial data port (default)

dac_DigPDN

0 – normal

1 – resets DAC DSM, DEM, filter and serial data port (default)

adc_stm_rst

0 – normal (default)

1 – reset ADC state machine to power down state

dac_stm_rst

0 – normal (default)

1 – reset DAC state machine to power down state

Revision 1.0

8/15/2009

ES8328 Datasheet(PDF) 13 Page - Suzhou Everest Semiconductor Co. Ltd.

ES8328 Datasheet(HTML) 13 Page - Suzhou Everest Semiconductor Co. Ltd.

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