ES8328 datasheet(21/37 Pages) EVEREST

Part #	ES8328

Description	Low Power Stereo Audio CODEC With Headphone Amplifier

PDF	37 Pages

Scroll/Zoom	100%

Manufacturer	EVEREST [Suzhou Everest Semiconductor Co. Ltd.]

Direct Link	http://www.everest-semi.com/en_index.html

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Everest Semiconductor

ES8328

6.2.13 Register 21 – ADC Control 13, Default 0000 0110

Bit Name

Bit

Description

ALCMODE

Determines the ALC mode of operation:

0 – ALC mode (Normal Operation)

1 – Limiter mode.

ALCZC

ALC uses zero cross detection circuit.

0 – disable (recommended)

1 – enable

TIME_OUT

Zero Cross time out

0 – disable (default)

1 – enable

WIN_SIZE

4:0

Windows size for peak detector，set the window size to N*16 samples

00110 – 96 samples (default)

00111 – 102 samples

…..

11111 – 496 samples

6.2.14 Register 22 – ADC Control 14, Default 0000 0000

Bit Name

Bit

Description

NGTH

7:3

Noise gate threshold

00000 – -76.5 dBFS

00001 – -75 dBFS

……

11110 – -31.5 dBFS

11111 – -30 dBFS

NGG

2:1

Noise gate type

x0 – PGA gain held constant

01 – mute ADC output

11 – reserved

NGAT

Noise gate function enable

0 – disable

1 – enable

6.3 DAC Control

6.3.1 Register 23 – DAC Control 1, Default 0000 0000

Bit Name

Bit

Description

DACLRSWAP

0 – normal

1 – left and right channel data swap

DACLRP

I2S, left justified or right justified mode:

Revision 1.0

8/15/2009

ES8328 Datasheet(PDF) 21 Page - Suzhou Everest Semiconductor Co. Ltd.

ES8328 Datasheet(HTML) 21 Page - Suzhou Everest Semiconductor Co. Ltd.

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