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LAN91C96-MS Datasheet(PDF) 44 Page - SMSC Corporation |
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LAN91C96-MS Datasheet(HTML) 44 Page - SMSC Corporation |
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44 / 125 page  Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Rev. 03-28-07 Page 44 SMSC LAN91C965v&3v DATASHEET TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared the LAN91C96 will complete the current transmission before stopping. When stopping due to an error, this bit is automatically cleared. Table 7.1 - Transmit Loop AUI FDSE FDUPLX EPH_LOOP LOOP LOOPS AT TRANSMITS TO NETWORK X X X 1 X EPH Block No X X 1 0 1 ENDEC No 1 0 1 0 0 Cable Yes 0 0 1 0 0 10BASE-T Driver Yes X 0 0 0 0 NORMAL CSMA/CD - No Loopback Yes X 1 1 0 0 FULL DUPLEX SWITCHED ETHERNET - No loopback and No SQET Yes I/O SPACE - BANK0 OFFSET NAME TYPE SYMBOL 2 EPH STATUS REGISTER READ ONLY EPHSR This register stores the status of the last transmitted frame. This register value, upon individual transmit packet completion, is stored as the first word in the memory area allocated to the packet. Packet interrupt processing should use the copy in memory as the register itself will be updated by subsequent packet transmissions. The register can be used for real time values (like TXENA and LINK OK). If TXENA is cleared the register holds the last packet completion status. TX UNRN LINK_ OK RES CTR _ROL EXC _DEF LOST CARR LATCOL WAKEUP 0 0 0 0 0 0 0 0 TX DEFR LTX BRD SQET 16COL LTX MULT MUL COL SNGL COL TX_SUC 0 0 0 0 0 0 0 0 TXUNRN - Transmit Under run. Set if Under run occurs, it also clears TXENA bit in TCR. Cleared by setting TXENA high. This bit should never be set under normal operation. LINK_OK - State of the 10BASE-T Link Integrity Test. A transition on the value of this bit generates an interrupt when the LE ENABLE bit in the Control Register is set. RES – This bit is reserved and will always return a zero(0). CTR_ROL - Counter Roll over. When set one or more 4 bit counters have reached maximum count (15). Cleared by reading the ECR register. EXC_DEF - Excessive deferral. When set last/current transmit was deferred for more than 1518 * 2 byte times. Cleared at the end of every packet sent. |
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