L640DU21NF datasheet(56/57 Pages) AMD

56 / 57 page

Am29LV640D/Am29LV641D

22366C6 January 22, 2007

D A TA

SH EET

Test Conditions

Test Conditions table: Redefined output timing mea-

surement reference level as 0.5 V

IO.

Added note to table and figure.

Erase and Program Operations table, Alternate

CE# Controlled Erase and Program Operations

table, Erase and Programming Performance table

Changed the typical sector erase time to 1.6 s.

AC Characteristics—Figure 15. Program

Operations Timing and Figure 17. Chip/Sector

Erase Operations

Deleted t

GHWL and changed OE# waveform to start at

high.

Physical Dimensions

Replaced figures with more detailed illustrations.

Revision B+1 (August 4, 2000)

Global

Added trademarks for SecSi Sector.

Accelerated Program Operation (page 11), Unlock

Bypass Command Sequence (page 25)

Added caution note regarding ACC pin.

Absolute Maximum Ratings

Corrected the maximum voltage on V

IO to +5.5V.

DC Characteristics table

Added WP# = V

IH to test conditions for standby cur-

rents I

CC3, ICC4, ICC5.

Revision B+2 (October 18, 2000)

Distinctive Characteristics

Corrected package options for 56-pin SSOP as being

available on Am29LV640DH/DL only.

Revision B+3 (January 18, 2001)

Global

Deleted “Preliminary” status from document.

General Description

In the second paragraph, corrected references to V

voltage ranges. The 90 and 120 speeds are available

where V

IO ≥ VCC, and 100 and 120 ns speeds are avail-

able where V

IO < VCC.

Revision B+4 (March 8, 2001)

Table 4, Sector Group Protection/Unprotection

Address Table

Corrected the sector group address bits for sectors

64–127.

Revision B+5 (October 11, 2001)

Connection Diagrams, Ordering Information,

Physical Dimensions

Added 64-ball Fortified BGA package information.

Revision B+6 (January 10, 2002)

Global

Clarified description of VersatileIO (V

IO) in the follow-

ing sections: Distinctive Characteristics; General De-

scription; VersatileIO (V

IO) Control; Operating Ranges;

DC Characteristics; CMOS compatible.

Reduced typical sector erase time from 1.6 s to 0.9 s.

DC Characteristics

Changed minimum V

OH1 from 0.85VIO to 0.8VIO. De-

leted reference to Note 6 for both V

OH1 and VOH2.

Erase and Program Performance table

Reduced typical sector erase time from 1.6 s to 0.9 s.

Changed typical chip program time from 90 s to 115 s.

Revision B+7 (April 15, 2002)

Ordering Information

Added N designator for Fortified BGA package mark-

ings.

Common Flash Interface (CFI)

Revised data value at address 44h. Clarified descrip-

tion of data for addresses 45–47h, 49, 4A, 4D–4Fh.

Table 10, Command Definitions

Clarified and combined Notes 4 and 5 into Note 4.

Revision B+8 (September 20, 2002)

Sector Erase Command Sequence

Changed sentence arrangement in fourth paragraph.

Revision B+9 (March 3, 2004)

Table 10, Command Definitions

Revised SecSi Sector Factory Protect (note 8) com-

mand definitions.

Revision B+10 (April 5, 2004)

Command Definitions

Changed first Address data for Erase Suspend/Re-

sume from BA to XXX.

Revision C (June 4, 2004)

Ordering Information

Added Pb-free OPNs.

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